UTCS Colloquium/Architecture: Rajit Manohar/Cornell University: "Managing Design Complexity in VLSI Systems" ACES 2.302, Tuesday, February 3, 2009 11:00 a.m.

Contact Name: 
Jenna Whitney
Feb 3, 2009 11:00am - 12:00pm

There is a sign up schedule for this event:



Type of Talk:  UTCS Co


 Speaker/Affiliation:  Rajit Manoha

r/Cornell University

Date/Time:  Tuesday, February 3, 2009&nb

sp; 11:00 a.m.

Location:  ACES 2.302

Host:  Steve


Talk Title:  "Managing Design Complexity in VLSI


Talk Abstract:

Abstract: Pre- and post-silicon

verification take up the majority of the design time of a modern VLSI syste

m. I will present an approach to managing this design complexity that is ba

sed on formal methods. This approach has been successfully applied to the d

esign of many complex  asynchronous VLSI systems including several mi

croprocessors that were correct on first silicon. I will present some of th

e key techniques  that allow this methodology to lead to a correct de

sign without sacrificing efficiency.

Speaker Bio:


Manohar is an Associate Professor of Electrical and Computer Engineering at
Cornell, where his group conducts research on asynchronous design. He rec

eived his B.S. (1994), M.S. (1995), and  Ph.D. (1998) from Caltech

, and has been on the Cornell faculty since 1998. He is the recipient of an
NSF CAREER award, three best paper awards, five teaching awards, and wa

s named to MIT technology review''s top 35 young innovators under 35. He is
a co-founder of Achronix Semiconductor, a fabless semiconductor company d

eveloping high-performance FPGAs.