UTCS Colloquium/Architecture: Srini Devadas/MIT: "A Search for an Efficient Reconfigurable Computing Substrate" ACES 2.402, Monday, April 20, 2009 2:00 p.m.

Contact Name: 
Jenna Whitney
Date: 
Apr 20, 2009 2:00pm - 3:00pm

There is a signup schedule for this event (UT EID required).

Type of

Talk:  UTCS Colloquium/Architecture

Speaker/Affiliation: 
Srini Devadas/MIT

Date/Time:  Monday, April 20, 2009 

2:00 p.m.

Location:  ACES 2.402

Host:  Derek Chiou<

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Talk Title: "A Search for an Efficient Reconfigurable Computing
Substrate"

Talk Abstract:

Computing substrates such as m

ulticore processor chips or Field Programmable Gate Arrays (FPGAs) share th

e characteristic of having two-dimensional arrays of processing elements in

terconnected by a routing fabric.  At one end of the spectrum, FPGAs
have a computing element that is a single-output programmable logic functi

on and a statically-configurable network of wires.  At the other end

, the computing element in a multicore is a complex 32-bit processor, and

processors are interconnected using a packet-switched network. 

We are designing a reconfigurable substrate that shares characterist

ics of both FPGAs and multicores.  Our substrate is configured to run
one application at a time, as with FPGAs. The computing element is a proc

essor, and processors are connected using an interconnection network with

virtual channel routers that use table-based routing. Bandwidth-sensitive o

blivious routing methods that statically allocate virtual channels to appli

cation flows utilize the network efficiently. To accommodate bursty flows,
the network contains adaptive bidirectional links that increase bandwidth

in one direction at the expense of another. We are in the process of buildi

ng a compiler that compiles applications onto this architecture so as to ma

ximize average throughput of the applications. Our plan is to use the compi

ler to refine the architecture and then to build a reconfigurable processor
chip.

Speaker Bio:

Srini Devadas is a Professor of Electrical

Engineering and Computer Science at the Massachusetts Institute of Technolo

gy (MIT), and has been on the faculty of MIT since 1988.  He current

ly serves as the Associate Head of Computer Science.  Devadas has wor

ked in the areas of Computer-Aided Design, testing, formal verification,
compilers for embedded processors, computer architecture, computer secur

ity, and computational biology and has co-authored numerous papers and boo

ks in these areas.  Devadas was elected a Fellow of the IEEE in 1998.

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-------------------------------------------------------------------------The Computer Architecture Seminar Series is sponsored jointly by the De

partments of Computer Science and Electrical & Computer Engineering an

d is supported by a grant from AMD.
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