Computer Architecture Seminar Series - Per Stenstrom/Chalmers University of Technology, "Scalability Challenges for Future Chip Multiprocessor Architectures", ACES 2.302

Contact Name: 
Jenna Whitney
Date: 
Feb 17, 2011 4:00pm - 5:00pm

There is a sign-up schedule for this event that can be found at

http://www.cs.utexas.edu/department/webevent/utcs/events/cgi/list_event

s.cgi

Type of Talk: Computer Architecture Seminar Series

Speaker/

Affiliation: Per Stenstrom/Chalmers University of Technology

Talk Audi

ence: UTCS Faculty, Grads, and Undergrads, Outside Interested Parties

Date/Time: Thursday, February 17, 2011, 4:00 p.m.

Location: ACES
2.302

Host: Kathryn McKinley (CS) and Yale Patt (ECE)

Talk Title

: Scalability Challenges for Future Chip Multiprocessor Architectures

Talk Abstract:
Technology forecasts predict a biennial doubling of the nu

mber of processor cores for the next ten years. But the road forward to unl

eash their computational power to applications will be increasingly challen

ging. Some of these challenges are: i) how can architects provide a more pr

oductive interface to the software? ii) How can the memory system be archit

ected so that memory bandwidth can scale up exponentially? iii) How can the
chip resources be used to make the whole chip infrastructure scalable to a
large number of processor cores. As for high-productivity hardware/softwar

e interfaces, I will talk about our recent contributions to realize hardwa

re transactional memory and the direction we are taking beyond that towards
a high-productivity hardware/software interface. Concerning memory systems
there is considerable room for improvement in the utilization of on-chip m

emory resources. I will present work-in-progress on our value-centric appro

ach in designing memory systems. Eventually, the serial bottleneck, so cl

everly framed by Amdahl decades back, will hit us. If there is time, I wi

ll also talk about a design-space exploration exercise we did in which we h

ave found that in some data mining applications that potentially scale to h

undreds of cores, reduction operations can limit scalability substantially

. Through validated analytical models, we find that while asymmetric chip

multiprocessors intuitively could mitigate these serial bottlenecks, symme

tric chip multiprocessors with more powerful cores appear to be a better pu

rsuit.

Speaker Bio:
Per Stenstrom is a professor of computer enginee

ring at Chalmers University of Technology since 1995. His research interest

s are devoted to design principles for high-performance computer systems an

d he has made multiple contributions to especially high-performance memory

systems. He has authored or co-authored three textbooks and more than a hun

dred publications in international journals and conferences. He is regularl

y serving program committees of major conferences in the computer architect

ure field. He is also an associate editor of IEEE Transactions on Parallel

and Distributed Processing Systems and associate editor-in-chief of the Jou

rnal of Parallel and Distributed Computing. He co-founded the HiPEAC Networ

k of Excellence funded by the European Commission. He has acted as general

and program chair for a large number of conferences including the ACM/IEEE

Int. Symposium on Computer Architecture, the IEEE High-Performance Compute

r Architecture Symposium, and the IEEE Int. Parallel and Distributed Proce

ssing Symposium. He is a Fellow of the ACM and the IEEE and a member of Aca

demia Europaea and the Royal Swedish Academy of Engineering Sciences.