UTCS Colloquium/Architecture: Lieven Eeckhout/Ghent University, Belgium "Per-Thread Cycle Accounting in SMT Processors" ACES 2.402, Thursday, April 30, 2009 2:00 p.m.

Contact Name: 
Jenna Whitney
Apr 30, 2009 2:00pm - 3:00pm

There is a signup schedule for this event (UT EID required).

Type o

f Talk:  UTCS Colloquium/Architecture


; Lieven Eeckhout/Ghent University, Belgium

Date/Time:  Thurs

day, April 30, 2009   3:30 p.m.

Location:  ACES 2


Host:  Lizy John

Talk Title:  "Per-Threa

d Cycle Accounting in SMT Processors"

Talk Abstract:


ltaneous Multi-threading (SMT) processors run multiple hardware threads sim

ultaneously on a single processor core. While this improves hardware utiliz

ation substantially, co-executing threads affect each other''s performance
in often unpredictable ways. System software however is unaware of these p

erformance interactions at the micro-architecture level, which may lead to
unfair scheduling at the system level.

Starting from a mechanis

tic performance model, we derive a cycle accounting architecture for Simul

taneous Multithreading (SMT) processors that estimates the execution times

for each of the threads had they been executed alone, while they are runni

ng simultaneously on the SMT processor. This is done by accounting each cyc

le to either a base, miss event or waiting cycle component. Single-threade

d alone execution time is then estimated as the sum of the base and miss ev

ent components; the waiting cycle component represents the lost cycle coun

t due to SMT execution. The cycle accounting architecture incurs reasonable
hardware cost (around 1KB of storage) and estimates single-threaded

erformance accurately with average prediction errors around 7.2% for two-pr

ogram workloads and 11.7% for four-program workloads.

The cycle

accounting architecture has several important applications to system softwa

re and its interaction with SMT hardware. For one, the estimated single-th

read alone execution time provides an accurate picture to system software o

f the actually consumed processor cycles per thread. The alone execution ti

me instead of the total execution time (timeslice) may make system software
scheduling policies more effective. Second, a new class of thread-progres

s aware SMT fetch policies based on per-thread progress indicators enable s

ystem software level priorities to be enforced at the hardware level. Third

, per-thread cycle accounting enables substantially more effective symbiot

ic job scheduling.

Speaker Bio:
Lieven Eeckhout is an assistant
professor at Ghent University, Belgium, and is a postdoctoral fellow wit

h the Fund for Scientific Research -- Flanders (FWO). He received his PhD d

egree in computer science and engineering from Ghent University in 2002. Hi

s main research interest include computer architecture, virtual machines,
performance modeling and analysis, simulation methodology, and workload

characterization. He has published papers in top conferences such as ISCA,
ASPLOS, HPCA, OOPSLA, PACT, CGO, DAC and DATE; he has served on mult

iple program committees including ISCA, PLDI, HPCA and IEEE Micro Top Pic

ks; and he is the program chair for ISPASS 2009. His work on hardware
performance counter architectures was selected by IEEE Micro Top Picks fro

m 2006 Computer Architecture Conferences as one of the "most signific

ant research publications in computer architecture based on novelty and ind

ustry relevance". He graduated 5 PhD students, and currently supervi

ses one postdoctoral researcher, 4 PhD students and 3 MSc students.