ibed that allows pipeline delays to be monitored and analyzed in detail. We
use this technique to measure the cost of each cache miss. The cost of a m

iss is displayed (graphed) as a histogram which represents a precise reado

ut showing a detailed visualization of the cost of each cache miss througho

ut all levels of the memory hierarchy. We call the graphs ''spectrograms%92
because they reveal certain signature characteristics of the processor %92

s memory hierarchy the pipeline and the miss pattern itself. Cache miss s

pectrograms are produced by analyzing misses according to the miss cluster

size and comparing instruction sequences and execution times that occurred
near the miss cluster in a ''finite cache''simulation run to the same set

of instructions and execution times in an ''infinite cache'' run then calc

ulating the difference in run times. We show that in a memory hierarchy wit

h N
cache levels (L1 L2 ... LN and memory) and a miss cluster of si

ze C there are (C+N) choose C possible clusters of miss penalties. This re

present all possible sums from all possible combinations of the miss latenc

ies from each level of the memory hierarchy (L2 L3 ... Memory) for a given
cluster size. Additionally a theory is presented that describes the shape
of a spectrogram and we use this theory to predict the shape of spectrogr

ams for larger miss clusters. Detailed
analysis of a spectrograph leads
to much greater insight in pipeline dynamics including effects due to pre

fetching and miss queueing delays.

Speaker Bio:
Thomas R. Puzak
received a B. S. in Mathematics and M. S. in Computer Science from the Uni

versity of Pittsburgh and a Ph. D. in Electrical and Computer Engineering f

rom the University of Massachusetts. Since joining IBM he has spent over th

irty years working in IBM Research. While at IBM he received Technical Achi

evement Outstanding Contribution and Innovation Awards served as Chairma

n of the Computer Architecture Special Interest Group at the T. J. Watson <

br>Research Center and holds more than 30 patents on processor and memory