UTCS Architecture: Dan Sorin Duke University Comprehensive Detection of Errors in Multithreaded Memory Systems ACES 2.402 Monday March 19 2007 at 3:30 p.m.

Contact Name: 
Jenna Whitney
Mar 19, 2007 3:30pm - 4:45pm

There is a signup schedule for this event.

Type of Talk: Ar


Speaker Name: Dan Sorin

Speaker Affiliation: Duk

e University

Date: Monday March 19 2007

Start Time: 3:30p


End Time: 4:45p.m.

Location: ACES 2.402

Host: S

teve Keckler

Talk Title: Comprehensive Detection of Errors in Multi

threaded Memory Systems

Talk Abstract:
Multithreaded architecture

s including multicore processors and multithreaded uniprocessors are beco

ming ubiquitous. Our goal is to detect all possible errors in the memory sy

stems of these machines without resorting to large amounts of expensive an

d power-hungry redundancy. Because correct operation of the memory system i

s defined by the memory consistency model we can detect errors by checking
if the observed memory system behavior deviates from the specified

sistency model. We have designed a framework for dynamic
verification o

f memory consistency (DVMC) and this framework applies to all existing com

mercial consistency models. Our DVMC framework consists of mechanisms to dy

namically verify three invariants that we have proven to be equivalent to m

emory consistency. We have developed an implementation of the framework for
the SPARCv9 architecture and we have experimentally evaluated its perform

ance using full-system
simulation of commercial workloads.


ker Bio:
Daniel J. Sorin is an assistant professor of Electrical and Com

puter Engineering and of Computer Science at Duke University. His research

interests include dependable computer architecture and system design. He re

ceived a PhD and MS in electrical and computer engineering from the Univers

ity of Wisconsin and he received a BSE in electrical engineering from Duke
University. He is the recipient of an NSF Career
Award and a Warren Fa

culty Scholarship at Duke.