Architecture: Jose Martinez Cornell University Core Fusion: Accommodating Software Diversity in Chip Multiprocessors ACES 2.402 Monday February 26 2007 at 3:30 p.m.

Contact Name: 
Jenna Whitney
Date: 
Feb 26, 2007 3:30pm - 4:45pm

There is a signup schedule for this event.

Speaker Name/

Affiliation: Jose Martinez Cornell University

Date/Time: Monday

February 26 2007 3:30 p.m. - 4:45 p.m.

Location: ACES 2.402
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br>Talk Abstract:
Chip multiprocessors (CMPs) hold the prospect of deliv

ering long-term performance growth by integrating more cores on the die wit

h each new technology generation. In the short term on-chip integration of
a few relatively large cores may yield sufficient throughput when running

multiprogrammed workloads. However harnessing the full potential of CMPs i

n the long term makes a broad adoption of parallel programming
inevitab

le.

We envision a CMP-dominated future where a diverse landscape of

software in different stages of parallelization exists at all times. Unfort

unately in this future the inherent rigidity in current proposals for CMP
designs makes it hard to come up with a universal CMP that can accommodate
this software diversity.

In this talk I will discuss Core Fusion a
CMP architecture where cores can fuse into larger cores on demand to execu

te sequential code very fast while still retaining the ability to operate

independently to run highly parallel code efficiently. Core Fusion builds u

pon a substrate of fundamentally independent cores and conventional memory

coherence/ consistency support and enables the CMP to dynamically morph in

to different configurations to adapt to the changing needs of software at r

un-time. Core Fusion does not require specialized software support it leve

rages mature micro-architecture technology and it can interface with the a

pplication through small
extensions encapsulated in ordinary paralleliz

ation libraries macros or directives.

Speaker Bio:
Jos%E9 Mar

t%EDnez (Ph.D.''02 Computer Science UIUC) is assistant professor of electr

ical and computer engineering and graduate field member of computer science
at Cornell University. He leads the M3 Architecture Research Group at Corn

ell whose interests include multicore architectures reconfigurable and se

lf-optimizing hardware and hardware-software interaction. Mart%EDnez''s wo

rk has been selected to IEEE Micro Top Picks twice (2003 and 2007). In 2005
he and his students received the Best Paper Award at HPCA-11 for their wo

rk on check pointed early load retirement. Mart%EDnez is also the recipient
of
a NSF CAREER Award and more recently an IBM Faculty Award. His te

aching responsibilities at Cornell include computer architecture at both un

dergraduate and graduate levels. He also organizes the AMD Computer Enginee

ring Lecture Series.