Colloquium: Matt Frank/University of Illinois Urbana-Champaign Microarchitectural Support for Automatic Parallelization ACES 2.302

Contact Name: 
Jenna Whitney
Jan 29, 2007 3:30pm - 4:45pm

Type of Talk: Colloquium

Speaker Name: Matt

Speaker Affiliation: Assist. Professor of Electrical & Compu

ter Engineering at University of Illinois-Urbana-Champaign.

Date: Mo

nday January 29 2007

Start Time: 3:30pm

Location: ACES 2.30


Host: Derek Chiou

Talk Title:Microarchitectural Support for
Automatic Parallelization

Talk Abstract:
This talk will describe
my group''s ongoing research on effectively
and practically paralleliz

ing general purpose programs to small
scale parallel systems (on the or

der of about 8 single-threaded superscalar cores). Our approach to this pro

blem has been careful
speculative parallelization. Data dependences are

learned dynamically
to avoid relying on brittle compiler analyses and

transformations but enforced conservatively to avoid the low probabilities
in techniques like value speculation. I will describe the co

techniques we use to find thread boundaries that allow complete c

ontrol independence of threads the dynamic slicing technique
we use to
implement an efficient dynamic dataflow engine and the
dependence pre

diciton mechanism we use to perform accurate pointer
analysis. Together
these mechanisms allow us to effectively parallelize general purpose progr

ams without dramatically increasing the number of instructions speculativel

y fetched or executed.

Speaker Bio:
Matthew Frank is an Assistant
Professor of Electrical and
Computer Engineering at the University of

Illinois at Urbana-Champaign. His degrees include a B.S. in Computer Scienc

e 1994 from the University of Wisconsin-Madison M.S. in Computer Scienc

e 1997 Massachusetts Institute of Technology and Ph.D. in Computer Scienc

e 2003 Massachusetts Institute of Technology. His research interests incl

ude Computer System Architecture and Compilers. He and his students are cur

rently designing PolyFlow an implicitly parallel architecture that automat

ically parallelizes programs as they run.