Architecture: Pierfrancesco Foglia/Universita di Pisa Way Adaptable D-Nuca Cache in ACES 2.402

Contact Name: 
Jenna Whitney
Sep 21, 2006 3:30pm - 4:00pm

There is a signup schedule for this event.


eaker Name/Affiliation: Pierfrancesco Foglia/Universita di Pisa


e/Time: Thursday September 21 2006 at 3:30 pm

Location: ACES 2.402

Host: Yale Patt

Talk Title: Way Adaptable D-Nuca Cache

Talk Abstract:
Power consumption is an increasing pressing problem
in the
design of high performance CPUs; Leakage or Static power willrapidly become a major source of such dissipation. Different

s to reduce static power consumption have been
developed in the research
environment. The Way Adaptable D-Nuca
cache represents the results of o

ur activity on applying such
techniques to large wire delay dominated

L2 caches. In a Way
Adaptable D-Nuca cache by exploiting typical featu

res of
D-NUCA design we dynamically activate or deactivate entire

ys on the basis of the application working set thus adapting
the size o

f the powered-on portion of L2 cache to the needs of
the running applica

tions. This imply a reduction of L2 cache
static power consumption with

negligible performance
degradation .and also some other little but perha

ps surprising

Speaker Bio:
Pierfrancesco Foglia i

s an Assistant Professor at the
Information Engineering Department of th

e University of Pisa.
His research interest lies in Computer Architectur

e including
Coherence Protocols Cache memories and Operating Systemeffects. His other research interests include Computer Networks
and Co

mputer Systems Usability. He has developed for Siemens
ICN a manager for
a network of GSM devices and in the
framework of the EU SPP project h

e defined coherence solutions
for a cartographic multiprocessor system.

He received his MS
and Ph.D. from the University of Pisa.