UTCS Architecture/UT VLSI Seminar Series: Dileep Bhandarkar/Intel Multi-Core Microprocessor Chips: Motivation & Challenges in ACES 2.302

Contact Name: 
Jenna Whitney
May 3, 2006 2:00pm - 3:00pm

Speaker Name/Affiliation: Dileep Bhandarkar/Intel

Talk Title: Multi-Core Microprocessor Chips: Motivation & Challeng


Date/Time: May 3 2006 at 2:00 p.m.

Location: ACES 2.302

Host: David Pan & Co-Sponsored by te UT VLSI Seminar Series (http:


Talk Abstract:
Advances in s

emiconductor process technology allow hundreds
of millions of transisto

rs to be integrated on a single
chip. Intel?s 90 nm technology Montecit

o chip was the first
billion transistor chip featuring dual cores and l

arge cache
in 2005. Nanotechnology that continues to drive Moore?s

Law provides a doubling of the transistor density every
two years. Mult

i-core chips will become common not only
in high-end servers but also i

n desktop and mobile PCs.

Multi-core processors present several chal

lenges related
to on-chip system architecture power management reliab

and software scaling. This talk will touch upon some of

e challenges and discuss some possible solutions.

Speaker Bio:

. Bhandarkar is an IEEE Fellow and a Distinguished Alumnus
of the Indi

an Institute of Technology Bombay where he
received his B. Tech in El

ectrical Engineering in 1970.
He also has a M.S. and Ph.D. in Electrica

l Engineering from
Carnegie Mellon University and has done graduate wo

rk in
Business Administration at the University of Dallas.

He is
currently Director of the Enterprise Architecture
Lab in processors an

d chipsets. He has been with Intel since
1995 and has managed system ar

chitecture and performance
analysis activities. Prior to joining Intel
he spent almost
18 years at Digital Equipment Corporation where he ma

processor and system architecture and performance analysis

ork related to the VAX Prism MIPS and Alpha architectures.
He also w

orked at Texas Instruments for 4 years in their
research labs in a vari

ety of areas including magnetic bubble
memories charge coupled devices
fault tolerant memories
and computer architecture.

Dr. Bhanda

rkar holds 15 U.S. Patents and has published more
than 30 technical pap

ers in various journals and conference
proceedings. He is also the auth

or of a book titled Alpha
Architecture and Implementations.