UTCS Unveiling the UT-Austin TRIPS Processor: An Architecture for Scaling to the End of Silicon

Contact Name: 
Jenna Whitney
Date: 
Apr 30, 2007 5:00pm - 6:00pm

UTCS Unveiling the UT-Austin TRIPS Processor
Date: Monday April 30 2007

Unveiling/Speakers: 5:00p.m. - 6:00
p.m.

Unveiling Location: ACES 2.302

By Invitation Reception
immediately following

Host: Department of Computer Sciences

Talk Title: UTCS Unveiling the UT-Austin TRIPS Processor:

An Architecture for Scaling to the End of Silicon

Talk Abstrac

t:
For the past seven years a research team led by Professors
Stephe

n Keckler Doug Burger and Kathryn McKinley in the
Department of Compu

ter Sciences at the University of Texas
at Austin has been designing a

radical new type of
polymorphous microprocessor architecture that can p

roduce
improved single-thread performance--at greater power efficiencie

s--
than conventional designs. This technology called Explicit Data
Graph Execution (EDGE architectures) offers a flexible alternative
to

the current industrial direction of providing a greater number
of proce

ssor cores with each passing generation.

Please attend the official

unveiling of the TRIPS prototype
processor a working system that demon

strates the
capabilities of this new EDGE technology. Produced with

generous support from DARPA each TRIPS prototype
processor contains tw

o processing cores each of which
can issue 16 operations per cycle wit

h up to 1 024
instructions in flight simultaneously. The prototype isthe first on a roadmap that will lead to ultra-powerful
flexible pro

cessors implemented in nanoscale technologies.