UTCS Colloquium/Architecture: Mateo Valero/Technical University of Catalonia: Supercomputing for the Future Supercomputing from the Past ACES 2.302 Monday February 11 2008 3:30 p.m.

Contact Name: 
Jenna Whitney
Date: 
Feb 11, 2008 3:30pm - 4:30pm

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Type of Talk: UTCS Colloquium/Architecture

Speaker/Affiliatio

n: Mateo Valero/Technical University of Catalonia

Date/Time: Monda

y February 11 2008 3:30 p.m.

Location: ACES 2.302

Host:

Yale Patt

Talk Title: Supercomputing for the Future Supercomputing
from the Past

Talk Abstract:
Supercomputers which were a long t

ime ago built on technology developed
from scratch are nowadays built f

rom commodity components. On one side
this means that designers of such
systems have to closely monitor the
evolution of mass market developmen

ts. On the other side supercomputing
becomes a driving boost for techno

logy and systems for the future providing
requirements for the performa

nce and design. As fundamental limits in the
single processor per chip

in terms of performance/power ratio are already on
the table multicore
chips and massive parallelism have become the trend to
achieve the requ

ired performance levels. A hierarchical structure both in
hardware and

software is the unavoidable approach build future
supercomputing system

s. The talk will first address how these systems have
been built in the

past and how we envisage their design in the near future.

The gap be

tween peak and real performance for current systems will become
worst if
designers don''t adopt a vertical approach from processor to node and

system design (including interconnect) parallel programming models dynami

c
resource management to improve load balancing tools for performanceanalysis prediction and optimization and new numerical methods algorit

hms
and applications. Research and proposals in this direction will be p

resented
during the talk in the framework of the future 10/100 Petaflops
architecture for
the Marenostrum site the Barcelona Supercomputing Cen

ter.

Speaker Bio:
Professor Valero was born in 1952 in a small to

wn in Aragon not far from
Zarazoga. He obtained his Telecommunication E

ngineering Degree from
the Technical University of Madrid (UPM) in 19

74 and his Ph.D. in
telecommunications from the Technical University o

f Catalonia (UPC) in
1980. He has been teaching at UPC since 1974. In 19

83 he bacame full
professor in the Computer Architecture Department. He
has served as Chair of
the Computer Architecture Department (1983-84 1

986-87 1989-90 and
2001-2005) and Dean of Computer Engineering School

(1984-85). Today he
is a Full Professor in the Department and has been

the founding Director
(since its inception in 2004) of the Barcelona Su

percomputer Center a 25
million dollar a year enterprise funded by the

governements of Spain and
Catalunya.

His research is in the area
of computer architecture with special emphasis on
high performance com

puters: processor organization memory hierarchy
systolic array proces

sors interconnection networks numerical algorithms
compilers and per

formance evaluation. He has co-authored over 400
publications: more than
250 in Conference and the rest in Journals and Book
Chapters. He has gr

aduated more than 30 PhDs in Computer Architecture 12
of whom are today
full professors at leading engineering departments in Spain.