rtar chips to mitigate these high fabrication costs while offering
the
performance and integration of a modern ASIC. This work
includes seve

ral architectural design choices and innovations
including a polymorph

ic on-chip network design. I will demonstrate
multiple modes of netwo

rk customization that this design allows
including topology and buffer

ing resources. This single polymorphic
network fabric can be configure

d to mimic the topology and perform-
ance of optimally designed applicat

ion-specific networks with no
appreciable overhead. This network is no

t only a critical enabler of
brick and mortar-based designs but has br

oad applicability to any
chip requiring an on-chip network. When used

with brick and mortar
however low-cost high-performance custom chip