UTCS Colloquium/Architecture: David Brooks/Harvard: Computer Design in the Nanometer Scale Era: Challenges and Solutions ACES 2.402 Monday September 8 2008 3:30 p.m.
There is a signup schedule for this event (UT EID required).
pe of Talk: UTCS Colloquium/Architecture
Date/Time: Monday September 8 2008 3:30 p.m.
Location: ACES 2.402
Host: Steve Keckler
Talk Title: C
omputer Design in the Nanometer Scale Era: Challenges and Solutions
Technology scaling has enabled tremendous growth
the computing industry over the past few decades.
However recent tren
ds in power dissipation reliability
thermal constraints and device v
ariability threaten to
limit the continued benefits of device scaling
performance improvements and cause increased
r in future technology generations.
The temporal and spatial scales of
motivate holistic solutions that span the circuit
rchitecture and software layers. In this talk I will
l ongoing projects that seek to address
technology scaling issues. Th
ese projects include efforts
in the areas of a) power and performance m
design space optimization for future chip-multiprocessor systems b) variability- tolerant design of memory hierarchies
) accelerator-based architectures for power/performance
e talk will also discuss our chip prototyping efforts
that support this
David Brooks joined Harvard University in Sep
tember of 2002
and is currently an Associate Professor of Computer Scie
Dr. Brooks received his B.S. (1997) degree from the University of Southern California and his M.A. (1999) and Ph.D (2001)
om Princeton University all in Electrical Engineering.
Prior to joini
ng Harvard University Dr. Brooks was a Research
Staff Member at the IB
M T.J. Watson Research Center. Dr.
Brooks received an IBM Faculty Part
nership Award in 2004
an NSF CAREER award in 2005 and a DARPA Young F
Award in 2007. His research interests include architecture and
software approaches to address power reliability and variability
issues for embedded and high-performance computer systems.
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