UTCS Colloquium/Architecture: Beeman Strong/Intel: Looking Inside Intel: the Core (Nehalem) Microarchitecture ACES 2.402 Monday October 20 2008 2:15 p.m.

Contact Name: 
Jenna Whitney
Date: 
Oct 20, 2008 2:15pm - 3:15pm

There is a signup schedule for this event (UT EID required).

T

ype of Talk: UTCS Colloquium

Speaker/Affiliation: Beeman Strong/Int

el

Date/Time: Monday October 20 2008 2:15 p.m.

Location:
ACES 2.402

Talk Title:
Looking Inside Intel: the Core (Nehalem)

Microarchitecture

Talk Abstract:
Intel''s next-generation microa

rchitecture (Nehalem)
represents the next step in processor energy effi

ciency
performance and dynamic scalability and was designed
from

the ground up to take advantage of hafnium-based
Intel%AE 45nm high-k m

etal gate silicon technology.

What you will learn from this session:

*Details behind key microarchitecture features including:

- Enhancements to the out-of-order execution engine

- Enhancem

ents to the platform bandwidth

- Enhancements to the cache subsy

stem

- Extensions to the instruction set with SSE4.2

*Des

cription of the power management innovations
on the next generation Int

el%AE microarchitecture
(Nehalem) family of processors including:
<

br> - Impact on typical and idle power consumption

- Implicat

ions to processor performance

Speaker Bio:
Beeman Strong received
his BS from UT in 1996.
He then spent 9+ years in architecture validat

ion
at Intel starting with the P4 (Willamette). He then
moved to t

he architecture team during the Nehalem
project in 2005 focusing i on

branch prediction
livelock breakers and virtualization. He is now the

branch predictor owner of Intel''s next core micro-
architecture.
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The Computer Architecture Seminar Series is sponsored jointly
by the
Departments of Computer Science and Electrical & Computer Engine

ering
and is supported by a grant from AMD.