UTCS Colloquium/Architecture: Beeman Strong/Intel: Looking Inside Intel: the Core (Nehalem) Microarchitecture ACES 2.402 Monday October 20 2008 2:15 p.m.
There is a signup schedule for this event (UT EID required).
ype of Talk: UTCS Colloquium
Speaker/Affiliation: Beeman Strong/Int
Date/Time: Monday October 20 2008 2:15 p.m.
Looking Inside Intel: the Core (Nehalem)
Intel''s next-generation microa
represents the next step in processor energy effi
performance and dynamic scalability and was designed
the ground up to take advantage of hafnium-based
Intel%AE 45nm high-k m
etal gate silicon technology.
What you will learn from this session:
*Details behind key microarchitecture features including:
- Enhancements to the out-of-order execution engine
ents to the platform bandwidth
- Enhancements to the cache subsy
- Extensions to the instruction set with SSE4.2
cription of the power management innovations
on the next generation Int
(Nehalem) family of processors including:
br> - Impact on typical and idle power consumption
ions to processor performance
Beeman Strong received
his BS from UT in 1996.
He then spent 9+ years in architecture validat
at Intel starting with the P4 (Willamette). He then
moved to t
he architecture team during the Nehalem
project in 2005 focusing i on
livelock breakers and virtualization. He is now the
branch predictor owner of Intel''s next core micro-
The Computer Architecture Seminar Series is sponsored jointly
Departments of Computer Science and Electrical & Computer Engine
and is supported by a grant from AMD.
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