UTCS Colloquium/Architecture: Kei Hiraki/University of Tokyo: GRAPE-DR Project: A Combination of Peta-Scale Computing and High-Speed Networking ACES 2.402 Monday November 17 2008 3:30 p.m.

Contact Name: 
Jenna Whitney
Date: 
Nov 17, 2008 3:30pm - 4:30pm

Type of Talk: UTCS Colloquium/Architecture

Speaker/Affiliation: Kei Hiraki/University of Tokyo

Date/Time: Mo

nday November 17 2008 3:30 p.m.

Location: ACES 2.402

Host

: Derek Chiou

Talk Title: GRAPE-DR Project: A Combination of Peta

-Scale
Computing and High-Speed Networking

Talk Abstract:
Th

e University of Tokyo and the National observatory of Japan
have been j

ointly developing a GRAPE-DR system which realize
a combination of Pet

a-Scale computing and very high-speed data-
sharing system for scientifi

c computing. In this talk we describe
the outline of GRAPE-DR project
architecture of the GRAPE-DR
processor and the methods used in Data-R

eservoir system which
is used to share data among distant research inst

itutes.

Main objectives of GRAPE-DR system are (1) realization of ve

ry
cost-effective and power-efficient computation (2) construction of a

practical peta-scale computing system for computation-intensive
scie

ntific applications. GRAPE-DR adopts different approach SIMD
architectu

re without interconnects between processing elements(PEs).
Figure 1 show

s block diagram of GRAPE-DR processor chip. All the
data transfer to an

d from PEs are achieved by broadcasting memory
and reduction network wi

th arithmetic units. This architecture is effective
to reduce the amoun

t of hardware. As shown in Table 1 the size of the
die is much smaller
than other chips for HPC systems such as nVIDIA
8800 or CELL.

GRAPE-DR chip is carefully designed to compute several important
applic

ations including n-body problem for galaxy generation molecular
dynamic

s quantum molecular simulation (e.g. FMO) dense linear
equations (e.g

. Linpack) and simulation in bio-informatics.

Speaker Bio:
Kei H

iraki is a Professor in the Department of Computer Science
Graduate Sc

hool of Information and Technology at the University
of Tokyo. He recei

ved a BA MS and Ph.D. in physics from the
University of Tokyo. He the

n worked in the Electrotechnical Laboratory
at MITI in Japan from 1982

until 1988. At this time he came to the USA
to work at IBM T.J. Watson

Research Center. In 1991 he returned to
Japan to be a professor at the
University of Tokyo.

Prof. Hiraki performed wide range of research

Topics including Dataflow
architecture Distributed Shared Memory Highl

y-parallel architecture
and very high-speed internet communication. H

e currently holds all the
classes of Internet2 Land Speed Records for h

igh-speed long-distance
TCP communications.

The Computer Archit

ecture Seminar Series is sponsored jointly by the
Departments of Compute

r Science and Electrical & Computer Engineering
and is supported by a

grant from AMD.