UTCS Colloquium/Architecture: Mark Horowitz/ Stanford University: "Why Design Must Change: Rethinking Digital Design," ACES 6.304, Monday, November 2, 2009, 11:00 a.m.

Contact Name: 
Jenna Whitney
Date: 
Nov 2, 2009 11:00am - 12:00pm

Type of Talk: UTCS Colloquium/ Architecture

Speaker/ A

ffiliation:  Mark Horowitz/ Stanford University

Date/Time:&nbsp

; Monday, November 2, 2009/ 11:00 a.m.

Location: ACES 6.304

Host: Steve Keckler

Talk Title:  "Why Design Must Change:

  Rethinking Digital Design"

Talk Abstract:
In the m

id 1980''s the power growth that accompanied scaling forced the industry to
focus on CMOS technology, and leave nMOS and bipolars for niche applicati

ons. Twenty years later, CMOS technology is facing power issues of its own

.  After first reviewing the "cause" of the problem, it

will become clear that there are not easy solutions this time -- no new tec

hnology or simple system/circuit change will rescue us.  Power, and

not number of devices is now the primary limiter of chip performance, and

the need to create power efficient designs is changing how we do design.&nb

sp; In the past this we would turn to specialized computation (ASICs) to c

reate the needed efficiency, but the rising NRE costs for chip design (now
over $10M/chip) has caused the number of ASIC design starts to fall not ri

se.

To get out of this paradox, we need to change the way we th

ink about chip design.  For many reasons I don''t believe that either
the current SoC, or high-level language effort will solve this problem. I

nstead, we should acknowledge that working out the interactions in a compl

ex design is complex, and will cost a lot of money, even when we do it we

ll.  So once we have worked it out, we want to leverage this over so

lution over a broader class of chips. We can accomplish this by creating a

"fixed" system architecture, but of very flexible components.&

nbsp; That is instead of building a programmable chip to meet
a broa

d class of application needs, you create a virtual programmable chip, tha

t is MUCH more flexible than any real chip.  The application designer
(the new chip designer) will then configure this substrate to optimize for
their application and then create that chip. To demonstrate how this might
work, we use a multiprocessor generator to create an customized CMP which
executes H.264 encode with an energy efficiency comparable to an ASIC.&nbs

p; As we show in this example for very low energy computation, DRAM energ

y can be any issue, and we will end the talk describing how to address thi

s final energy frontier.

Speaker Bio:
Mark Horowitz is the

Chair of the Electrical Engineering Department and the Yahoo! Founders Prof

essor of the School of Engineering at Stanford University. In addition he i

s Chief Scientist at Rambus Inc. He received his BS and MS in Electrical En

gineering from MIT in 1978, and his PhD from Stanford in 1984. Dr. Horowit

z has received many awards including a 1985 Presidential Young Investigator
Award, the 1993 ISSCC Best Paper Award, the ISCA 2004 Most Influential P

aper of 1989, and the 2006 Don Pederson IEEE Technical Field Award. 
He is a fellow of IEEE and ACM and is a member of the National Academy of

Engineering and the American Academy of Arts and Science.

Dr. Ho

rowitz''s research interests are quite broad and span using EE and CS analy

sis methods to problems in molecular biology to creating new design methodo

logies for analog and digital VLSI circuits.  He has worked on many p

rocessor designs, from early RISC chips to creating some of the first dist

ributed shared memory multiprocessors, and is currently working on on-chip
multiprocessor designs.  Recently he has worked on a number of probl

ems in computational photograph. In 1990, he took leave from Stanford to h

elp start Rambus Inc, a company designing high-bandwidth memory interface

technology, and has continued work in high-speed I/O at Stanford. His curr

ent research includes multiprocessor design, low power circuits, high-spe

ed links,
computational photography, and applying engineering to bi

ology.

 

-----------------------------------------------

--------------------------------
The Computer Architecture Seminar Ser

ies is sponsored jointly by the
Departments of Computer Science and El

ectrical & Computer Engineering 
and is supported by a gra

nt from IBM.

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Parking for

off-campus visitors: We suggest that you park in the San Jacinto
parki

ng garage (formerly PG1) at 24th & San Jacinto.  Parking validat

ion will
be available. Please contact the host for this seminar or sto

p by the
refreshment cart to have your parking validated.

S

ubmap including San Jacinto Parking Garage:
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