UTCS Colloquium/Architecture-Steve Reinhardt/AMD Research: "End-to-End Critical Path Analysis," ACES 2.402, Monday, December 14, 2009, 3:30 p.m.

Contact Name: 
Jenna Whitney
Date: 
Dec 14, 2009 3:30pm - 4:30pm

There is a sign-up schedule for this event that can be found
at http://www.cs.utexas.edu/department/webeven

t/utcs/events/cgi/list_events.cgi

Type of Talk: UTCS Collo

quium/Architecture

Speaker/Affiliation: Steve Reinhardt/AMD Re

search

Date/Time: Monday, December 14, 2009, 3:30 p.m.

Location: ACES 2.402

Host: Kathryn McKinley

Ta

lk Title: End-to-End Critical Path Analysis

Talk Abstract:

Many important workloads today, such as web-hosted services, are
lim

ited not by processor core performance but by interactions among
the c

ores, the memory system, I/O devices, and the complex software
laye

rs that tie these components together. Identifying performance
bottlen

ecks is difficult because, as in any concurrent system,
overheads in
one component may be hidden due to overlapping with other
operations.

Critical path analysis is a well-known approach to identifying<

br />bottlenecks in highly
concurrent systems. However, building dep

endence graphs for this
analysis typically requires detailed domain kn

owledge, making it
difficult to apply across all the hardware and sof

tware components in
a system. We address this problem by developing a
straightforward
methodology for identifying end-to-end critical paths
across software
and simulated hardware in complex networked systems.
By modeling
systems as collections of state machines interacting via

queues, we
can trace critical paths through multiplexed processing en

gines,
identify when resources create bottlenecks (including abstract

resources such as flow-control credits), and predict the benefit of<

br />eliminating bottlenecks by increasing hardware speeds or expanding
available resources.

We implement our technique in a full-syst

em simulator, instrumenting a
TCP microbenchmark, a web server, the
Linux TCP/IP stack, and a
simulated Ethernet controller. From a sin

gle run of the
microbenchmark, our tool--within minutes--correctly id

entifies a
series of bottlenecks, and predicts the performance of hyp

othetical
systems in which these bottlenecks are successively eliminat

ed,
potentially saving hours or days of head scratching and repeated<

br />simulations.

This is joint work with Ali Saidi (ARM), Nate
Binkert (HP Labs), and
Trevor Mudge (Michigan).

Speak

er Bio:

Steven K. Reinhardt is a Fellow in AMD''s Research and Adv

anced
Development Labs, where he is investigating future system

architectures. Steve is also is an Adjunct Associate Professor at the

University of Michigan. From 2006 to 2008, Steve was at Reservoir
La

bs, Inc., where he managed the development of a DoE-sponsored
networ

k processor-based high-speed intrusion-prevention system. From
1997 th

rough 2006 he was a full-time faculty member at University of
Michigan

, researching system architectures for high-performance TCP/IP
networ

king, cache and memory system design, multithreading, and
processor
reliability.