UTCS Distinguished Lecture Series-David J. Kuck/Intel: "Computational Capacity: Uses in Hardware-Software Codesign and Software Performance Enhancement," ACES 2.302, Friday, April 30, 2010, 1:00 p.m.

Contact Name: 
Jenna Whitney
Apr 30, 2010 1:00pm - 2:00pm

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Type of Talk: UTCS Distinguished Lecture Series


ation: David J. Kuck/Intel

Date/Time: Friday, April 30, 2010, 1:00


Location: ACES 2.302

Host: Keshav Pingali

Talk Title: C

omputational Capacity: Uses in Hardware-Software Codesign and Software Per

formance Enhancement

Talk Abstract:

Performance stability has lon

g been a major parallel and sequential computing problem. Apparently small

application changes on a given machine, or architectural changes for a giv

en application, can yield surprisingly large performance changes. How can

we improve the design process to produce systems with more predictable perf

ormance characteristics? The computational capacity model is designed to do
this by fast design space exploration, using a wide representation of app


Large regions of the 3-D codesign space representing hardwa

re (HW) cost (in terms of bandwidth and power), system performance, and S

W load variation can be explored simultaneously via capacity-based codesign

. The method is much faster than current simulation methods used for system
design. Also, performance enhancement insight about when program transfor

mations will help and by how much, can be derived from the model. Some res

ults obtained from prototype implementations of this algebraic model will b

e presented.

We define Ci,j, the computational capacity of a compute

r HW node i, as the amount of the node''s bandwidth used in computational

phase j. Using HW parameters for a given system, together with correspondi

ng measured Ci,j values for a collection of SW phases, a comprehensive co

design equation can be written. This equation can be used in HW design by h

olding SW capacity ratios invariant. By holding HW parameters invariant, c

apacity inequalities and the codesign equation can be used as a guide to pe

rformance enhancement for a set of applications.

Speaker Bio:


id J. Kuck is an Intel Fellow, Software and Services Group, and Director

of the Parallel and Distributed Solutions Division (PDSD). David was previ

ously part of Intel''s Enterprise Platforms Group and Director of the KAI S

oftware Lab, a leading provider of performance-oriented compilers and prog

ramming tools used in the development of multithreaded applications. Kuck

founded KAI in 1979 and is an emeritus faculty member of the Computer Scien

ce and Electrical and Computer Engineering departments of the University of
Illinois at Urbana-Champaign. He also served as director of the Center fo

r Supercomputing Research and Development.

Kuck holds a bachelor''s de

gree in electrical engineering from the University of Michigan as well as a
master''s degree and Ph.D. in engineering from Northwestern University. H

e is a fellow of the American Association for the Advancement of Science,

the Association for Computing Machinery, and the Institute of Electrical a

nd Electronics Engineers. He is also a member of the National Academy of E