Computer Architecture Seminar Series - Murali Annavaram/University of Southern California, "WearMon: Ultra Low Cost Wearout Monitoring for Detecting Processor Aging", ACES 2.302

Contact Name: 
Jenna Whitney
Feb 28, 2011 3:30pm - 4:30pm

There is a sign-up schedule for this event that can be found at


Type of Talk: Computer Architecture Seminar Series


Affiliation: Murali Annavaram/University of Southern California

Talk A

udience: UTCS Faculty, Grads and Undergrads, and Outside Interested Parti


Date/Time: Monday, February 28, 2011, 3:30 p.m.

Location: A

CES 2.302

Host: Kathryn McKinley (CS) and Lizy John (ECE)

Talk Ti

tle: WearMon: Ultra Low Cost Wearout Monitoring for Detecting Processor Agi


Talk Abstract:
As process technology shrinks, circuits experienc

e accelerated wearout. Monitoring wearout will be critical to improve the e

fficiency of error detection and correction approaches. In this talk I will
describe WearMon an adaptive critical path monitoring architecture which p

rovides accurate and real-time measure of the processor''s timing margin de

gradation. Special test patterns check a set of critical paths in the circu

it-under-test. By activating the actual devices and signal paths used in no

rmal operation of the chip, each test will capture up-to-date timing margi

n of these paths. While WearMon is highly efficient in the common case ther

e are two factors that cause WearMon costs to rise. First, industrial desi

gns may have steep critical path walls. Second, circuit wearout depends on
process variations, circuit operation conditions, and runtime path utili

zation. Dynamic nature of wearout coupled with steep critical path walls ma

ke selection of a group of paths to be monitored a challenging task. In the
second part of the talk we will describe a novel cross-layer framework tha

t combines application layer information with design time modifications to

provide near zero cost monitoring.

Speaker Bio:
Murali Annavaram is

an Assistant Professor in the Electrical Engineering department at USC. Pri

or to his appointment at USC, he gained significant industrial experience

working first at Intel research on hardware design and then at Nokia resear

ch on mobile phone technologies for a total of 6 years. His work on Energy-

Per- Instruction throttling at Intel is implemented in Intel Core i7 proces

sor to turbo boost performance at a fixed power budget. His work on Virtual

-Trip-Lines at Nokia formed the foundation for Nokia Traffic Works product

that provides real time traffic sensing using mobile phones. Murali''s rese

arch at USC spans energy efficiency in mobile devices and reliability in se

rver architectures (more info on his website

p/). Murali is a recipient of NSF CAREER award in 2010. His passion is a co

mbination of teaching, working with his graduate students and traveling. M

urali received his Ph.D. from the University of Michigan.