UTCS Colloquia - Steve Blackburn/Australian National University, "Looking Back on the Language and Hardware Revolutions: Measured Power, Performance, and Scaling", ACES 2.402

Contact Name: 
Jenna Whitney
Date: 
Mar 9, 2011 4:30pm - 6:30pm

Type of Talk:

Speaker/Affiliation: Steve Blackburn/Austra

lian National University

Talk Audience: UTCS Faculty, Grads, Undergr

ads, and Outside Interested Parties

Date/Time: Wednesday, March 9,

2011, 4:30 p.m.

Location: ACES 2.402

Host: Kathryn McKinley

nTalk Title: Looking Back on the Language and Hardware Revolutions: Measure

d Power, Performance, and Scaling

Talk Abstract:
This talk reports
and analyzes measured chip power and performance on
five process technol

ogy generations executing 61 diverse benchmarks
with a rigorous methodolo

gy. We measure representative Intel IA32
processors with technologies ran

ging from 130nm to 32nm while they
execute sequential and parallel benchm

arks written in native and
managed languages. During this period, hardw

are and software changed
substantially: (1) hardware vendors delivered ch

ip multiprocessors
instead of uniprocessors, and independently (2) softw

are developers
increasingly chose managed languages instead of native lan

guages.
This quantitative data reveals the extent of some known and previ

ously
unobserved hardware and software trends. Two themes emerge.

(

I) Workload: The power, performance, and energy trends of native
worklo

ads do not approximate managed workloads. For example, (a)
SPECcpu nati

ve benchmarks on the i7 and i5 draw significantly less
power than managed
or scalable native benchmarks; and (b) managed
runtimes exploit paralle

lism even when running single-threaded
applications. The results recomme

nd architects always include native
and managed workloads when designing

and evaluating energy efficient
hardware.

(II) Architecture: Clock s

caling, microarchitecture, simultaneous
multithreading, and chip multi

processors each elicit a huge variety of
power, performance, and energy
responses. This variety and the
difficulty of obtaining power measureme

nts recommends exposing on-chip
power meters and when possible structure

specific power meters for
cores, caches, and other structures. Just as
hardware event counters
provide a quantitative grounding for performance
innovations, power
meters are necessary for optimizing energy.

Spe

aker Bio:
Steve Blackburn is an Associate Professor in the Computer Scien

ce Department at Australian National University in Australia. His research

interests centered on the challenge of making software run faster and more

power-efficiently on modern hardware. His primary interests include: micro

architectural support for managed languages, fast and efficient garbage co

llection, and the design and implementation of virtual machines. As a bac

kdrop to this, he has a longstanding interest in role of sound methodology
and infrastructure in successful research innovation.