Programming Languages Lunch Colloquia - Peter Hofstee/IBM, "Towards shared-memory reconfigurable computing," PAI 3.14
Type of Talk: Programming Languages Lunch Colloquium
Speaker/Affiliation: Peter Hofstee/IBM
Talk Audience: UTCS Faculty and Grads
Date/Time: 11/5/12, 12:00pm - 1:30pm
Location: PAI 3.14
Host: Keshav Pingali
Talk Title: "Towards shared-memory reconfigurable computing"
Talk Abstract: In this talk we describe some recent prototype systems that combine conventional Power processors with reconfigurable acceleration (FPGAs). The goal of this work is to create systems that allow us to accelerate "single thread" computations and also to improve efficiency for throughput computing. Ultimately, the goal of this work is to enable an infrastructure in which the reconfigurable logic is as easy to program and to use as conventional processors. We discuss an organization that maintains architectural integrity and lay out some of the challenges, most specifically to the runtimes of such processors. We also discuss the role of some recent efforts, such as OpenCL for FPGAs and LiMe in the context of this broader objective.
Speaker Bio: H. Peter Hofstee was born in the Netherlands and received his doctor's degree in theoretical physics from the Rijksuniversiteit Groningen, The Netherlands, in 1988. In 1994 he earned his PhD from Caltech, afterwards he spent two years on the faculty.
Hofstee joined the IBM Austin Research Laboratory in 1996, where he worked on the world's first GHz CMOS microprocessor prototype (i.e., the IBM Rivina) and other high-performance microprocessor designs. In mid 2000, Hofstee joined the team to develop the concept of the Cell Broadband Engine, which is the central processing unit of the PlayStation 3, and has already found a number of other uses. He is currently the chief architect of the Synergistic Processor Element (SPE) of the Cell microprocessor. Hofstee has more than 30 issued patents and over 60 patents pending, most of them Cell related.
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