Programming Languages Lunch - Ardavan Pedram, UTCS, "Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics"
Talk Audience: UTCS Faculty, Grads, Undergrads, Other Interested Parties
Talk Abstract: The primary concern in future architectures is power/energy efficiency. Full-custom design of application-specific IPs can yield up to two orders of magnitude better power efficiency over conventional general-purpose cores. However, a tremendous design effort is required in integrating a new accelerator for each new application.
In this talk, I present the design of a specialized Linear Algebra Processor~(LAP) architecture that maintains the efficiency of full custom hardware while providing enough flexibility to execute a whole class of coarse-grain operations.
I further verify that this architecture can perform a broad range of matrix-matrix operations as complex as matrix factorizations, and even Fast Fourier Transforms~(FFTs), while maintaining its ASIC level efficiency. Such process requires expertise and careful codesign of the algorithms and the architecture.
I present a power-performance model that compares state-of-the-art CPUs and GPUs with our design and reveals the sources of inefficiencies. When compared to other conventional architectures for linear algebra applications and FFT, our LAP is over an order of magnitude better in terms of power efficiency. Based on our estimations, up to 55 and 25 GFLOPS/W single- and double-precision efficiencies are achievable on a single chip in standard 45nm technology.
For the list of publications and more information please visit my homepage at http://www.cs.utexas.edu/~ardavan/
Speaker Bio: Ardavan Pedram is a postdoctoral research fellow at the University of Texas at Austin. He received his PhD in computer engineering from the University of Texas at Austin in 2013 under supervision of Robert van de Geijn and Andreas Gerstlauer. His research interests include high performance computing and computer architecture. He specifically works on hardware-software co-design (algorithm for architecture) of special purposed accelerators for high-performance energy-efficient linear algebra and signal processing applications.
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