My research interest is in the area of Microarchitecture. Specifically, I am focusing on solving the memory latency problem in future microprocessor designs. The gap between the CPU's and the main memory's performance is a key performance bottleneck in today's microarchitecture. In simple words, the main memory cannot feed data to the CPU at a good enough pace to keep it busy all the time. The CPU ends up stalling most of the time, waiting for the data it needs to process.
Caches have been successful to some extent in bridging this gap by buffering recently used data in high speed (more expensive) memory elements. Prefetchers aim to improve the cache efficiency by predicting what data elements the CPU will need in the near future and fetching them from the main memory into the cache ahead of time. This ensures that when the CPU needs the data, it is readily available in the cache and the processor does not have to wait for the main memory to service the request.Prefetching has been a widely studied problem and some interesting papers in the area are posted below. My focus as of now is to understand the limitations of modern day prefetchers and think of ways to make prefetchers more efficient in the context of multi-core systems.
I have been exploring statistical and data mining techniques to better understand the nature of memory accesses made by programs. The insights gained from this analysis will help us understand the shortcomings present in the runtime system and the micro-architecture that make it hard to exploit the underlying memory access patterns in programs. Eventually, we aim to co-design the micro-architecture and the runtime system in such a way that memory accesses can be predicted effectively in order to lower memory access latency.