Scalable On-chip Interconnect Topologies.
B. Grot and S. W. Keckler. CMP-MSI: 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects, 2008.

Regional Congestion Awareness for Load Balance in Networks on a Chip.
P. Gratz, B. Grot and S. W. Keckler. The 14th International Symposium on Computer Architecture (HPCA), 2008.
Acceptance rate: 20%

Good Memories: Enhancing Memory Performance for Precise Flow Tracking.
B. Grot and W. Mangione-Smith. Advanced Networking and Communications Hardware Workshop (ANCHOR), 2005.