Bertrand A. MaherDepartment of Computer Science
University of Texas at Austin
My Curriculum Vitae
I graduated with my Ph.D. in August 2010! I'm now a software engineer with Intel Corporation, developing next-generation compiler and architecture technologies to address challenges in power and performance.
Broadly speaking, I am interested in architecture, compilers, and programming languages. Since those three topics cover a good chunk of systems research, I'll narrow it down a bit: I'm interested in the direction that computer architecture will take now that frequency scaling has largely ended and power limitations are limiting the application of conventional techniques for increasing instruction-level parallelism. To meet this challenge, we'll need a combination of efficient architectures; languages that allow programmers to express parallelism, whether explicitly or implicitly; and compilers that can generate efficient code to manage this parallelism.
In my dissertation research, I've investigated how best to build a compiler for an efficient parallel architecture. Explicit Data Graph Execution architectures, exemplified by the TRIPS processor and the TFlex microarchitecture, allow the compiler to specify inter-instruction communication within large blocks of instructions. The processor fetches and commits these blocks atomically and sequentially, which makes it easy to program using existing high-level languages like C. Since blocks are central to efficient execution on such processors, my research has focused on compiler algorithms and policies for creating blocks, and on developing microarchitectural techniques for executing blocks efficiently.
- Evolving Compiler Heuristics to Manage Communication and Contention (AAAI 2010, Nectar Track)
M. Taylor, K. Coons, B. Robatmili, B. Maher, D. Burger, K. McKinley
- An Evaluation of the TRIPS Computer System (ASPLOS 2009)
M. Gebhart, B. Maher, K. Coons, J. Diamond, P. Gratz, M. Marino, N. Ranganathan, B. Robatmili, A. Smith, J. Burrill, S. Keckler, D. Burger, K. McKinley
Best Paper Award
- Feature Selection and Policy Optimization for Distributed Instruction Placement Using Reinforcement Learning (PACT 2008)
K. Coons, B. Robatmili, M. Taylor, B. Maher, D. Burger, K. McKinley
- Merging Head and Tail Duplication for Convergent Hyperblock Formation (MICRO 2006)
B. Maher, A. Smith, D. Burger, K. McKinley
- Compiling for EDGE Architectures (CGO 2006)
A. Smith, J. Burrill, J. Gibson, B. Maher, N. Nethercote, B. Yoder, D. Burger, K. McKinley
- Scaling Power and Performance via Processor Composability (IEEE Transactions on Computers)
M.S. Govindan, B. Robatmili, D. Li, B. Maher, A. Smith, S. Keckler, D. Burger
- The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors (INTERACT 2011)
B. Maher, K. Coons, K. McKinley, D. Burger
- Software Infrastructure and Tools for the TRIPS Prototype (MOBS 2007)
B. Yoder, J. Burrill, et al.
- Evaluation and Optimization of Signal Processing Kernels on the TRIPS Architecture (ODES 2006)
K. Bush, M. Gebhart, E. Wei, N. Yudin, B. Maher, N. Nethercote, D. Burger, S. Keckler
- Optimal Huffman Tree-Height Reduction for Instruction-Level Parallelism (TR-08-34)
K. Coons, W. Hunt, B. Maher, D. Burger, K. McKinley
- Best Paper Award at ASPLOS 2009 for "An Evaluation of the TRIPS Computer System"
- Microelectronics and Computer Development Fellowship, 2004
- College of Natural Sciences Dean's Excellence Award, 2004
University of Texas at Austin, August 2010
Advisors: Doug Burger and Kathryn McKinley
M.S. in Computer Science
University of Texas at Austin, May 2007
B.S. in Electrical Engineering and Computer Science
Yale University, May 2004
Intel Corporation, Software Engineer, October 2010 - present
I'm working on hardware/software co-design, binary translation, and dynamic compilation.
Sun Microsystems Labs, Research Intern, Summer 2009
At Sun, I worked on Project Portmeirion, which has the goal of implementing complex commercial ISAs such as x64 and SPARC using dynamic translation. I implemented support for x86 SSE floating point in the front-end of the Portmeirion JIT compiler, and in the process realized that we would need an industrial strength testing harness to ensure correctness. The front-end tester that I developed uses a code-coverage approach to explore the entire space of opcodes, and compares the results of virtualized execution with native execution.
Intel Corporation, Research Intern, Summer 2008
I worked with the Pin group to develop tools for finding runtime differences in nondeterministic programs. The approach I developed dynamically instruments two running processes, and produces lightweight control- and data-flow traces for online or offline comparison. Finding these differences can be a powerful debugging tool, both for isolating nondeterministic bugs, and for quickly finding errors in simulators by comparing execution to hardware.