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\begin{verbatim}#|
 Copyright (C) 1985 by Warren A. Hunt, Jr.  All Rights Reserved.

 You may copy and distribute verbatim copies of this Nqthm-1992 event script as
 you receive it, in any medium, including embedding it verbatim in derivative
 works, provided that you conspicuously and appropriately publish on each copy
 a valid copyright notice "Copyright (C) 1985 by Warren A. Hunt, Jr.  All
 Rights Reserved."

 NO WARRANTY

 Warren A. Hunt, Jr. PROVIDES ABSOLUTELY NO WARRANTY.  THE EVENT SCRIPT IS
 PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
 INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND
 FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND
 PERFORMANCE OF THE SCRIPT IS WITH YOU.  SHOULD THE SCRIPT PROVE DEFECTIVE, YOU
 ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.

 IN NO EVENT WILL Warren A. Hunt, Jr. BE LIABLE TO YOU FOR ANY DAMAGES, ANY
 LOST PROFITS, LOST MONIES, OR OTHER SPECIAL, INCIDENTAL OR CONSEQUENTIAL
 DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THIS SCRIPT (INCLUDING BUT
 NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES
 SUSTAINED BY THIRD PARTIES), EVEN IF YOU HAVE ADVISED US OF THE POSSIBILITY OF
 SUCH DAMAGES, OR FOR ANY CLAIM BY ANY OTHER PARTY.

|#

;;; -*- Mode: LISP; Base: 10; Syntax: Zetalisp -*-

;   The Mechanical Verification of the FM8501 Microprocessor

;                             by
;                       Warren A. Hunt, Jr.



\end{verbatim}
\noindent{\sc Event}:   Start with the initial {\bf thm} theory.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                             lemmas about PLUS                                ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}
\noindent{\sc Event}:   For efficiency, compile those definitions not yet compiled.

\addvspace{18pt}
\begin{tabbing}{\sc Theorem}:  plus-1 \\ \index{plus-1}
({\tt{1}} $+$ {\it{x\/}}) $=$ ($1\;+$ {\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  plus-right-id \\ \index{plus-right-id}
({\it{y\/}} $\not\in\;${\bf{N}}${}$) $\rightarrow$ (({\it{x\/}} $+$ {\it{y\/}}) $=$ {\rm{fix}}\,({\it{x\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  plus-add1 \\ \index{plus-add1}
\=\+({\it{x\/}} $+$ ($1\;+$ {\it{y\/}})) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{y\/}} $\in\;${\bf{N}}${}$$\;\;${\bf then }$1\;+$ ({\it{x\/}} $+$ {\it{y\/}}) \\ 
{\bf else }$1\;+$ {\it{x\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  commutativity2-of-plus \\ \index{commutativity2-of-plus}
({\it{x\/}} $+$ ({\it{y\/}} $+$ {\it{z\/}})) $=$ ({\it{y\/}} $+$ ({\it{x\/}} $+$ {\it{z\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  commutativity-of-plus \\ \index{commutativity-of-plus}
({\it{x\/}} $+$ {\it{y\/}}) $=$ ({\it{y\/}} $+$ {\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  associativity-of-plus \\ \index{associativity-of-plus}
(({\it{x\/}} $+$ {\it{y\/}}) $+$ {\it{z\/}}) $=$ ({\it{x\/}} $+$ ({\it{y\/}} $+$ {\it{z\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  plus-equal-0 \\ \index{plus-equal-0}
(({\it{a\/}} $+$ {\it{b\/}}) $=$ {\tt{0}}) $=$ (({\it{a\/}} $\simeq {\tt{0}}$) $\wedge$ ({\it{b\/}} $\simeq {\tt{0}}$))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  plus-cancellation \\ \index{plus-cancellation}
(({\it{a\/}} $+$ {\it{b\/}}) $=$ ({\it{a\/}} $+$ {\it{c\/}})) $=$ ({\rm{fix}}\,({\it{b\/}}) $=$ {\rm{fix}}\,({\it{c\/}}))
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                             lemmas about TIMES                               ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Theorem}:  times-zero2 \\ \index{times-zero2}
({\it{y\/}} $\not\in\;${\bf{N}}${}$) $\rightarrow$ (({\it{x\/}} $*$ {\it{y\/}}) $=$ {\tt{0}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  distributivity-of-times-over-plus \\ \index{distributivity-of-times-over-pl!us}
({\it{x\/}} $*$ ({\it{y\/}} $+$ {\it{z\/}})) $=$ (({\it{x\/}} $*$ {\it{y\/}}) $+$ ({\it{x\/}} $*$ {\it{z\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  times-add1 \\ \index{times-add1}
\=\+({\it{x\/}} $*$ ($1\;+$ {\it{y\/}})) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{y\/}} $\in\;${\bf{N}}${}$$\;\;${\bf then }{\it{x\/}} $+$ ({\it{x\/}} $*$ {\it{y\/}}) \\ 
{\bf else }{\rm{fix}}\,({\it{x\/}})$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  commutativity-of-times \\ \index{commutativity-of-times}
({\it{x\/}} $*$ {\it{y\/}}) $=$ ({\it{y\/}} $*$ {\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  commutativity2-of-times \\ \index{commutativity2-of-times}
({\it{x\/}} $*$ ({\it{y\/}} $*$ {\it{z\/}})) $=$ ({\it{y\/}} $*$ ({\it{x\/}} $*$ {\it{z\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  associativity-of-times \\ \index{associativity-of-times}
(({\it{x\/}} $*$ {\it{y\/}}) $*$ {\it{z\/}}) $=$ ({\it{x\/}} $*$ ({\it{y\/}} $*$ {\it{z\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  equal-times-0 \\ \index{equal-times-0}
(({\it{x\/}} $*$ {\it{y\/}}) $=$ {\tt{0}}) $=$ (({\it{x\/}} $\simeq {\tt{0}}$) $\vee$ ({\it{y\/}} $\simeq {\tt{0}}$))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  times-1 \\ \index{times-1}
({\tt{1}} $*$ {\it{x\/}}) $=$ {\rm{fix}}\,({\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  equal-bools \\ \index{equal-bools}
\=\+((({\it{bool1\/}} $=$ {\bf{t}}) $\vee$ ({\it{bool1\/}} $=$ {\bf{f}})) $\wedge$ (({\it{bool2\/}} $=$ {\bf{t}}) $\vee$ ({\it{bool2\/}} $=$ {\bf{f}}))) \\ 
$\rightarrow$$\;\;\;\;$(({\it{bool1\/}} $=$ {\it{bool2\/}}) $=$ (({\it{bool1\/}} $\rightarrow$ {\it{bool2\/}}) $\wedge$ ({\it{bool2\/}} $\rightarrow$ {\it{bool1\/}})))\-
\end{tabbing}


\noindent{\sc Event}:   Disable equal-bools.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  lessp-times \\ \index{lessp-times}
(({\it{y\/}} $*$ {\it{x\/}}) $<$ ({\it{x\/}} $*$ {\it{z\/}})) $=$ (({\it{x\/}} $\not\simeq {\tt{0}}$) $\wedge$ ({\it{y\/}} $<$ {\it{z\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  times-2-not-1 \\ \index{times-2-not-1}
({\tt{2}} $*$ {\it{x\/}}) $\not=$ {\tt{1}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  lessp-crock1 \\ \index{lessp-crock1}
(({\it{z\/}} $+$ ({\tt{2}} $*$ {\it{v\/}} $*$ {\it{w\/}})) $<$ {\it{w\/}}) $=$ (({\it{v\/}} $\simeq {\tt{0}}$) $\wedge$ ({\it{z\/}} $<$ {\it{w\/}}))
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                             lemmas about EXP                                 ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{exp} \\  
\=\+{\rm{exp}}\,({\it{i\/}}, {\it{j\/}})\index{exp} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{j\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\tt{1}} \\ 
{\bf else }{\it{i\/}} $*$ {\rm{exp}}\,({\it{i\/}}, {\it{j\/}} $-\;1$)\index{exp}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  exp-plus \\ \index{exp-plus}
{\rm{exp}}\,({\it{i\/}}, {\it{j\/}} $+$ {\it{k\/}})\index{exp} $=$ ({\rm{exp}}\,({\it{i\/}}, {\it{j\/}})\index{exp} $*$ {\rm{exp}}\,({\it{i\/}}, {\it{k\/}})\index{exp})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  exp-of-0 \\ \index{exp-of-0}
\=\+{\rm{exp}}\,({\tt{0}}, {\it{k\/}})\index{exp} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{k\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\tt{1}} \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  exp-of-1 \\ \index{exp-of-1}
{\rm{exp}}\,({\tt{1}}, {\it{k\/}})\index{exp} $=$ {\tt{1}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  exp-by-0 \\ \index{exp-by-0}
{\rm{exp}}\,({\it{x\/}}, {\tt{0}})\index{exp} $=$ {\tt{1}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  exp-times \\ \index{exp-times}
{\rm{exp}}\,({\it{i\/}} $*$ {\it{j\/}}, {\it{k\/}})\index{exp} $=$ ({\rm{exp}}\,({\it{i\/}}, {\it{k\/}})\index{exp} $*$ {\rm{exp}}\,({\it{j\/}}, {\it{k\/}})\index{exp})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  exp-2-never-0 \\ \index{exp-2-never-0}
{\tt{0}} $<$ {\rm{exp}}\,({\tt{2}}, {\it{i\/}})\index{exp}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                           lemmas about DIFFERENCE                            ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Theorem}:  difference-elim \\ \index{difference-elim}
(({\it{y\/}} $\in\;${\bf{N}}${}$) $\wedge$ ({\it{y\/}} $\not<$ {\it{x\/}})) $\rightarrow$ (({\it{x\/}} $+$ ({\it{y\/}} $-$ {\it{x\/}})) $=$ {\it{y\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-2 \\ \index{difference-2}
({\it{x\/}} $-$ {\tt{2}}) $=$ (({\it{x\/}} $-\;1$) $-\;1$)
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-x-x \\ \index{difference-x-x}
({\it{x\/}} $-$ {\it{x\/}}) $=$ {\tt{0}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-plus \\ \index{difference-plus}
(({\it{j\/}} $+$ {\it{x\/}}) $-$ {\it{j\/}}) $=$ {\rm{fix}}\,({\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-plus-cancellation \\ \index{difference-plus-cancellation}
(({\it{a\/}} $+$ {\it{x\/}}) $-$ ({\it{a\/}} $+$ {\it{y\/}})) $=$ ({\it{x\/}} $-$ {\it{y\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  pathological-difference \\ \index{pathological-difference}
({\it{x\/}} $<$ {\it{y\/}}) $\rightarrow$ (({\it{x\/}} $-$ {\it{y\/}}) $=$ {\tt{0}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-crock1 \\ \index{difference-crock1}
\=\+(({\it{x\/}} $+$ ({\it{y\/}} $-$ {\it{z\/}})) $-$ {\it{y\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{y\/}} $<$ {\it{z\/}}$\;\;${\bf then }{\it{x\/}} $-$ {\it{y\/}} \\ 
{\bf else }{\it{x\/}} $-$ {\it{z\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-difference \\ \index{difference-difference}
(({\it{x\/}} $-$ {\it{y\/}}) $-$ {\it{z\/}}) $=$ ({\it{x\/}} $-$ ({\it{y\/}} $+$ {\it{z\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  lessp-difference \\ \index{lessp-difference}
(({\it{x\/}} $-$ {\it{y\/}}) $<$ {\it{x\/}}) $=$ (({\it{x\/}} $\not\simeq {\tt{0}}$) $\wedge$ ({\it{y\/}} $\not\simeq {\tt{0}}$))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-add1 \\ \index{difference-add1}
\=\+(($1\;+$ {\it{x\/}}) $-$ {\it{y\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{y\/}} $<$ ($1\;+$ {\it{x\/}})$\;\;${\bf then }$1\;+$ ({\it{x\/}} $-$ {\it{y\/}}) \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                       lemmas about QUOTIENT and REMAINDER                    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Theorem}:  remainder-quotient \\ \index{remainder-quotient}
(({\it{x\/}} ${}${\bf{mod}}${}$ {\it{y\/}}) $+$ ({\it{y\/}} $*$ ({\it{x\/}} $\div$ {\it{y\/}}))) $=$ {\rm{fix}}\,({\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-by-1 \\ \index{remainder-by-1}
({\it{y\/}} ${}${\bf{mod}}${}$ {\tt{1}}) $=$ {\tt{0}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-by-nonnumber \\ \index{remainder-by-nonnumber}
({\it{x\/}} $\not\in\;${\bf{N}}${}$) $\rightarrow$ (({\it{y\/}} ${}${\bf{mod}}${}$ {\it{x\/}}) $=$ {\rm{fix}}\,({\it{y\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  lessp-remainder \\ \index{lessp-remainder}
(({\it{x\/}} ${}${\bf{mod}}${}$ {\it{y\/}}) $<$ {\it{y\/}}) $=$ ({\it{y\/}} $\not\simeq {\tt{0}}$)
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-quotient-elim \\ \index{remainder-quotient-elim}
(({\it{y\/}} $\not\simeq {\tt{0}}$) $\wedge$ ({\it{x\/}} $\in\;${\bf{N}}${}$)) $\rightarrow$ ((({\it{x\/}} ${}${\bf{mod}}${}$ {\it{y\/}}) $+$ ({\it{y\/}} $*$ ({\it{x\/}} $\div$ {\it{y\/}}))) $=$ {\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-x-x \\ \index{remainder-x-x}
({\it{x\/}} ${}${\bf{mod}}${}$ {\it{x\/}}) $=$ {\tt{0}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-plus \\ \index{remainder-plus}
(({\it{j\/}} $+$ {\it{x\/}}) ${}${\bf{mod}}${}$ {\it{j\/}}) $=$ ({\it{x\/}} ${}${\bf{mod}}${}$ {\it{j\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-plus-times \\ \index{remainder-plus-times}
(({\it{x\/}} $+$ ({\it{i\/}} $*$ {\it{j\/}})) ${}${\bf{mod}}${}$ {\it{j\/}}) $=$ ({\it{x\/}} ${}${\bf{mod}}${}$ {\it{j\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-plus-times-commuted \\ \index{remainder-plus-times-commuted}
(({\it{x\/}} $+$ ({\it{j\/}} $*$ {\it{i\/}})) ${}${\bf{mod}}${}$ {\it{j\/}}) $=$ ({\it{x\/}} ${}${\bf{mod}}${}$ {\it{j\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-times \\ \index{remainder-times}
(({\it{j\/}} $*$ {\it{i\/}}) ${}${\bf{mod}}${}$ {\it{j\/}}) $=$ {\tt{0}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-add1-times \\ \index{remainder-add1-times}
(($1\;+$ ({\it{j\/}} $*$ {\it{i\/}})) ${}${\bf{mod}}${}$ {\it{j\/}}) $=$ ({\tt{1}} ${}${\bf{mod}}${}$ {\it{j\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  quotient-plus-times \\ \index{quotient-plus-times}
\=\+(({\it{x\/}} $+$ ({\it{i\/}} $*$ {\it{j\/}})) $\div$ {\it{j\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{j\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }{\it{i\/}} $+$ ({\it{x\/}} $\div$ {\it{j\/}})$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  quotient-plus-times-commuted \\ \index{quotient-plus-times-commuted}
\=\+(({\it{x\/}} $+$ ({\it{j\/}} $*$ {\it{i\/}})) $\div$ {\it{j\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{j\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }{\it{i\/}} $+$ ({\it{x\/}} $\div$ {\it{j\/}})$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  quotient-times \\ \index{quotient-times}
\=\+(({\it{j\/}} $*$ {\it{i\/}}) $\div$ {\it{j\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{j\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }{\rm{fix}}\,({\it{i\/}})$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  quotient-add1-times \\ \index{quotient-add1-times}
\=\+(($1\;+$ ({\it{j\/}} $*$ {\it{i\/}})) $\div$ {\it{j\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{j\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }{\it{i\/}} $+$ ({\tt{1}} $\div$ {\it{j\/}})$\;${\bf  endif}\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable times.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  times-distributes-over-remainder \\ \index{times-distributes-over-remainde!r}
(({\it{x\/}} $*$ {\it{y\/}}) ${}${\bf{mod}}${}$ ({\it{x\/}} $*$ {\it{z\/}})) $=$ ({\it{x\/}} $*$ ({\it{y\/}} ${}${\bf{mod}}${}$ {\it{z\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-of-1 \\ \index{remainder-of-1}
\=\+({\tt{1}} ${}${\bf{mod}}${}$ {\it{x\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} $=$ {\tt{1}}$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }{\tt{1}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-crock1 \\ \index{remainder-crock1}
\=\+(({\it{x\/}} $\in\;${\bf{N}}${}$) $\wedge$ ({\it{x\/}} $<$ {\it{z\/}}) $\wedge$ ({\it{v\/}} $\in\;${\bf{N}}${}$) $\wedge$ ({\it{z\/}} $\in\;${\bf{N}}${}$) $\wedge$ ({\it{z\/}} $\not=$ {\tt{0}})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+(($1\;+$ (({\tt{2}} $*$ {\it{x\/}}) $+$ ({\tt{2}} $*$ {\it{v\/}} $*$ {\it{z\/}}))) ${}${\bf{mod}}${}$ ({\tt{2}} $*$ {\it{z\/}})) \\ 
$=$$\;\;\;\;$($1\;+$ ({\tt{2}} $*$ {\it{x\/}})))\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  times-2-distributes-over-remainder-add1 \\ \index{times-2-distributes-over-remain!der-add1}
(($1\;+$ ({\tt{2}} $*$ {\it{y\/}})) ${}${\bf{mod}}${}$ ({\tt{2}} $*$ {\it{z\/}})) $=$ ($1\;+$ ({\tt{2}} $*$ ({\it{y\/}} ${}${\bf{mod}}${}$ {\it{z\/}})))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-crock2 \\ \index{remainder-crock2}
\=\+({\it{v\/}} $<$ {\rm{exp}}\,({\tt{2}}, {\it{size\/}} $-\;1$)\index{exp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+(\=\+(({\tt{2}} $*$ {\it{v\/}}) $+$ ({\tt{2}} $*$ {\it{w\/}} $*$ {\rm{exp}}\,({\tt{2}}, {\it{size\/}} $-\;1$)\index{exp})) \\ 
${}${\bf{mod}}${}$$\;\;\;\;$({\tt{2}} $*$ {\rm{exp}}\,({\tt{2}}, {\it{size\/}} $-\;1$)\index{exp}))\- \\ 
$=$$\;\;\;\;$({\tt{2}} $*$ {\it{v\/}}))\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-crock3 \\ \index{remainder-crock3}
\=\+(({\it{x\/}} $+$ ({\it{y\/}} $-$ {\it{z\/}})) ${}${\bf{mod}}${}$ {\it{y\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }({\it{x\/}} $+$ ({\it{y\/}} $-$ {\it{z\/}})) $<$ {\it{y\/}}$\;\;${\bf then }{\it{x\/}} $+$ ({\it{y\/}} $-$ {\it{z\/}}) \\ 
{\bf elseif }{\it{y\/}} $<$ {\it{z\/}}$\;\;${\bf then }{\it{x\/}} ${}${\bf{mod}}${}$ {\it{y\/}} \\ 
{\bf else }({\it{x\/}} $-$ {\it{z\/}}) ${}${\bf{mod}}${}$ {\it{y\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-of-0 \\ \index{remainder-of-0}
({\tt{0}} ${}${\bf{mod}}${}$ {\it{x\/}}) $=$ {\tt{0}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-crock4 \\ \index{remainder-crock4}
\=\+(($1\;+$ ({\it{x\/}} $+$ ({\it{y\/}} $-$ {\it{z\/}}))) ${}${\bf{mod}}${}$ {\it{y\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }($1\;+$ ({\it{x\/}} $+$ ({\it{y\/}} $-$ {\it{z\/}}))) $<$ {\it{y\/}}$\;\;${\bf then }$1\;+$ ({\it{x\/}} $+$ ({\it{y\/}} $-$ {\it{z\/}})) \\ 
{\bf elseif }{\it{y\/}} $<$ {\it{z\/}}$\;\;${\bf then }($1\;+$ {\it{x\/}}) ${}${\bf{mod}}${}$ {\it{y\/}} \\ 
{\bf elseif }{\it{z\/}} $<$ ($1\;+$ {\it{x\/}})$\;\;${\bf then }($1\;+$ ({\it{x\/}} $-$ {\it{z\/}})) ${}${\bf{mod}}${}$ {\it{y\/}} \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  quotient-2i-by-2 \\ \index{quotient-2i-by-2}
((($1\;+$ ({\it{i\/}} $+$ {\it{i\/}})) $\div$ {\tt{2}}) $=$ {\rm{fix}}\,({\it{i\/}})) $\wedge$ ((({\it{i\/}} $+$ {\it{i\/}}) $\div$ {\tt{2}}) $=$ {\rm{fix}}\,({\it{i\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  remainder-2i-by-2 \\ \index{remainder-2i-by-2}
((($1\;+$ ({\it{i\/}} $+$ {\it{i\/}})) ${}${\bf{mod}}${}$ {\tt{2}}) $=$ {\tt{1}}) $\wedge$ ((({\it{i\/}} $+$ {\it{i\/}}) ${}${\bf{mod}}${}$ {\tt{2}}) $=$ {\tt{0}})
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                           boolean operations                                 ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{xor} \\  
\=\+{\rm{xor}}\,({\it{x\/}}, {\it{y\/}})\index{xor} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} \\ 
{\bf then }\=\+{\bf if }{\it{y\/}}$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\- \\ 
{\bf elseif }{\it{y\/}}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\bf{f}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-not} \\  
\=\+{\rm{b-not}}\,({\it{x\/}})\index{b-not} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}}$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-nand} \\  
\=\+{\rm{b-nand}}\,({\it{x\/}}, {\it{y\/}})\index{b-nand} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} \\ 
{\bf then }\=\+{\bf if }{\it{y\/}}$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\- \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-nor} \\  
\=\+{\rm{b-nor}}\,({\it{x\/}}, {\it{y\/}})\index{b-nor} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}}$\;\;${\bf then }{\bf{f}} \\ 
{\bf elseif }{\it{y\/}}$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-and}$\;\;$
{\rm{b-and}}\,({\it{x\/}}, {\it{y\/}})\index{b-and} $=$ ({\it{x\/}} $\wedge$ {\it{y\/}})
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-or}$\;\;$
{\rm{b-or}}\,({\it{x\/}}, {\it{y\/}})\index{b-or} $=$ ({\it{x\/}} $\vee$ {\it{y\/}})
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-xor} \\  
\=\+{\rm{b-xor}}\,({\it{x\/}}, {\it{y\/}})\index{b-xor} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} \\ 
{\bf then }\=\+{\bf if }{\it{y\/}}$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\- \\ 
{\bf elseif }{\it{y\/}}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\bf{f}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-equv} \\  
\=\+{\rm{b-equv}}\,({\it{x\/}}, {\it{y\/}})\index{b-equv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} \\ 
{\bf then }\=\+{\bf if }{\it{y\/}}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\bf{f}}$\;${\bf  endif}\- \\ 
{\bf elseif }{\it{y\/}}$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{boolp}$\;\;$
{\rm{boolp}}\,({\it{x\/}})\index{boolp} $=$ ({\rm{truep}}\,({\it{x\/}}) $\vee$ {\rm{falsep}}\,({\it{x\/}}))
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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\end{verbatim}
\noindent{\sc Event}:   Add the shell {\it{bitv\/}}\index{bitv}, with bottom object function symbol {\it{btm\/}}, with recognizer function symbol {\it{bitvp\/}}, and 2 accessors: {\it{bit\/}}, with type restriction (one-of truep falsep) and default value false; {\it{vec\/}}, with type restriction (one-of bitvp) and default value btm.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  boolp-bit \\ \index{boolp-bit}
{\rm{boolp}}\,({\rm{bit}}\,({\it{x\/}})\index{bit})\index{boolp}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{fix-bv} \\  
\=\+{\rm{fix-bv}}\,({\it{x\/}})\index{fix-bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{x\/}})\index{bitvp}$\;\;${\bf then }{\it{x\/}} \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{carry} \\  
\=\+{\rm{carry}}\,({\it{c\/}})\index{carry} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{c\/}}$\;\;${\bf then }{\tt{1}} \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{size} \\  
\=\+{\rm{size}}\,({\it{a\/}})\index{size} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }$1\;+$ {\rm{size}}\,({\rm{vec}}\,({\it{a\/}})\index{vec})\index{size}$\;${\bf  endif}\- \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{trunc} \\  
\=\+{\rm{trunc}}\,({\it{a\/}}, {\it{n\/}})\index{trunc} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{trunc}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\it{n\/}} $-\;1$)\index{trunc})\index{bitv}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{compl} \\  
\=\+{\rm{compl}}\,({\it{x\/}})\index{compl} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{x\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{x\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,($\neg$ {\rm{bit}}\,({\it{x\/}})\index{bit}, {\rm{compl}}\,({\rm{vec}}\,({\it{x\/}})\index{vec})\index{compl})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim}; IT MAY BE POSSIBLE TO ELIMINATE THE C FLG.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{incr} \\  
\=\+{\rm{incr}}\,({\it{c\/}}, {\it{x\/}})\index{incr} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{x\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{x\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{xor}}\,({\it{c\/}}, {\rm{bit}}\,({\it{x\/}})\index{bit})\index{xor}, {\rm{incr}}\,({\it{c\/}} $\wedge$ {\rm{bit}}\,({\it{x\/}})\index{bit}, {\rm{vec}}\,({\it{x\/}})\index{vec})\index{incr})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bitn} \\  
\=\+{\rm{bitn}}\,({\it{x\/}}, {\it{n\/}})\index{bitn} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\bf{f}} \\ 
{\bf elseif }{\it{n\/}} $=$ {\tt{1}}$\;\;${\bf then }{\rm{bit}}\,({\it{x\/}})\index{bit} \\ 
{\bf else }{\rm{bitn}}\,({\rm{vec}}\,({\it{x\/}})\index{vec}, {\it{n\/}} $-\;1$)\index{bitn}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{btmp} \\  
\=\+{\rm{btmp}}\,({\it{a\/}})\index{btmp} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp}$\;\;${\bf then }{\it{a\/}} $=$ {\sc{btm}}\index{btm} \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{all-zerosp} \\  
\=\+{\rm{all-zerosp}}\,({\it{a\/}})\index{all-zerosp} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }($\neg$ {\rm{bit}}\,({\it{a\/}})\index{bit}) $\wedge$ {\rm{all-zerosp}}\,({\rm{vec}}\,({\it{a\/}})\index{vec})\index{all-zerosp}$\;${\bf  endif}\- \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{all-onesp} \\  
\=\+{\rm{all-onesp}}\,({\it{a\/}})\index{all-onesp} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\rm{bit}}\,({\it{a\/}})\index{bit} $\wedge$ {\rm{all-onesp}}\,({\rm{vec}}\,({\it{a\/}})\index{vec})\index{all-onesp}$\;${\bf  endif}\- \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-of-trunc \\ \index{size-of-trunc}
{\rm{size}}\,({\rm{trunc}}\,({\it{a\/}}, {\it{n\/}})\index{trunc})\index{size} $=$ {\rm{fix}}\,({\it{n\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-of-compl \\ \index{size-of-compl}
{\rm{size}}\,({\rm{compl}}\,({\it{a\/}})\index{compl})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-of-incr \\ \index{size-of-incr}
{\rm{size}}\,({\rm{incr}}\,({\it{c\/}}, {\it{a\/}})\index{incr})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  incr-f-noop \\ \index{incr-f-noop}
{\rm{incr}}\,({\bf{f}}, {\it{a\/}})\index{incr} $=$ {\rm{fix-bv}}\,({\it{a\/}})\index{fix-bv}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-0 \\ \index{size-0}
({\rm{size}}\,({\it{x\/}})\index{size} $=$ {\tt{0}}) $=$ {\rm{btmp}}\,({\it{x\/}})\index{btmp}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;            Definitions about logical functions                               ;;
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\end{verbatim}\begin{tabbing}{\sc Definition}:\index{v-not} \\  
\=\+{\rm{v-not}}\,({\it{a\/}})\index{v-not} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,($\neg$ {\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{v-not}}\,({\rm{vec}}\,({\it{a\/}})\index{vec})\index{v-not})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-or} \\  
\=\+{\rm{v-or}}\,({\it{a\/}}, {\it{b\/}})\index{v-or} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{bit}}\,({\it{a\/}})\index{bit} $\vee$ {\rm{bit}}\,({\it{b\/}})\index{bit}, {\rm{v-or}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{vec}}\,({\it{b\/}})\index{vec})\index{v-or})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-and} \\  
\=\+{\rm{v-and}}\,({\it{a\/}}, {\it{b\/}})\index{v-and} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{bit}}\,({\it{a\/}})\index{bit} $\wedge$ {\rm{bit}}\,({\it{b\/}})\index{bit}, {\rm{v-and}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{vec}}\,({\it{b\/}})\index{vec})\index{v-and})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-xor} \\  
\=\+{\rm{v-xor}}\,({\it{a\/}}, {\it{b\/}})\index{v-xor} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{xor}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{bit}}\,({\it{b\/}})\index{bit})\index{xor}, {\rm{v-xor}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{vec}}\,({\it{b\/}})\index{vec})\index{v-xor})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-not} \\  
\=\+{\rm{bv-not}}\,({\it{a\/}})\index{bv-not} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{b-not}}\,({\rm{bit}}\,({\it{a\/}})\index{bit})\index{b-not}, {\rm{bv-not}}\,({\rm{vec}}\,({\it{a\/}})\index{vec})\index{bv-not})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-or} \\  
\=\+{\rm{bv-or}}\,({\it{a\/}}, {\it{b\/}})\index{bv-or} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{b-or}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{bit}}\,({\it{b\/}})\index{bit})\index{b-or}, {\rm{bv-or}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{vec}}\,({\it{b\/}})\index{vec})\index{bv-or})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-and} \\  
\=\+{\rm{bv-and}}\,({\it{a\/}}, {\it{b\/}})\index{bv-and} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{b-and}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{bit}}\,({\it{b\/}})\index{bit})\index{b-and}, {\rm{bv-and}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{vec}}\,({\it{b\/}})\index{vec})\index{bv-and})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-xor} \\  
\=\+{\rm{bv-xor}}\,({\it{a\/}}, {\it{b\/}})\index{bv-xor} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{b-xor}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{bit}}\,({\it{b\/}})\index{bit})\index{b-xor}, {\rm{bv-xor}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{vec}}\,({\it{b\/}})\index{vec})\index{bv-xor})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;                 TC numbers and their operations                              ;;
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\end{verbatim}\begin{tabbing}{\sc Definition}:\index{tcp} \\  
{\rm{tcp}}\,({\it{x\/}})\index{tcp} $=$ (({\it{x\/}} $\in\;${\bf{N}}${}$) $\vee$ ({\rm{negativep}}\,({\it{x\/}}) $\wedge$ ({\rm{negative-guts}}\,({\it{x\/}}) $\not\simeq {\tt{0}}$)))
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{tc-in-rangep} \\  
\=\+{\rm{tc-in-rangep}}\,({\it{x\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\bf{f}} \\ 
{\bf elseif }{\rm{negativep}}\,({\it{x\/}})$\;\;${\bf then }{\rm{exp}}\,({\tt{2}}, {\it{n\/}} $-\;1$)\index{exp} $\not<$ {\rm{negative-guts}}\,({\it{x\/}}) \\ 
{\bf else }{\it{x\/}} $<$ {\rm{exp}}\,({\tt{2}}, {\it{n\/}} $-\;1$)\index{exp}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{add} \\  
\=\+{\rm{add}}\,({\it{x\/}}, {\it{y\/}})\index{add} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{negativep}}\,({\it{x\/}}) \\ 
{\bf then }\=\+{\bf if }{\rm{negativep}}\,({\it{y\/}})$\;\;${\bf then }$-$ ({\rm{negative-guts}}\,({\it{x\/}}) $+$ {\rm{negative-guts}}\,({\it{y\/}})) \\ 
{\bf elseif }{\it{y\/}} $<$ {\rm{negative-guts}}\,({\it{x\/}})$\;\;${\bf then }$-$ ({\rm{negative-guts}}\,({\it{x\/}}) $-$ {\it{y\/}}) \\ 
{\bf else }{\it{y\/}} $-$ {\rm{negative-guts}}\,({\it{x\/}})$\;${\bf  endif}\- \\ 
{\bf elseif }{\rm{negativep}}\,({\it{y\/}}) \\ 
{\bf then }\=\+{\bf if }{\it{x\/}} $<$ {\rm{negative-guts}}\,({\it{y\/}})$\;\;${\bf then }$-$ ({\rm{negative-guts}}\,({\it{y\/}}) $-$ {\it{x\/}}) \\ 
{\bf else }{\it{x\/}} $-$ {\rm{negative-guts}}\,({\it{y\/}})$\;${\bf  endif}\- \\ 
{\bf else }{\it{x\/}} $+$ {\it{y\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  commutativity2-of-add \\ \index{commutativity2-of-add}
{\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\it{z\/}})\index{add})\index{add} $=$ {\rm{add}}\,({\it{y\/}}, {\rm{add}}\,({\it{x\/}}, {\it{z\/}})\index{add})\index{add}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  commutativity-of-add \\ \index{commutativity-of-add}
{\rm{add}}\,({\it{x\/}}, {\it{y\/}})\index{add} $=$ {\rm{add}}\,({\it{y\/}}, {\it{x\/}})\index{add}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  associativity-of-add \\ \index{associativity-of-add}
{\rm{add}}\,({\rm{add}}\,({\it{x\/}}, {\it{y\/}})\index{add}, {\it{z\/}})\index{add} $=$ {\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\it{z\/}})\index{add})\index{add}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  add-with-carry-of-negatives-is-negative \\ \index{add-with-carry-of-negatives-is-!negative}
\=\+({\rm{tcp}}\,({\it{x\/}})\index{tcp} $\wedge$ {\rm{tcp}}\,({\it{y\/}})\index{tcp} $\wedge$ {\rm{negativep}}\,({\it{x\/}}) $\wedge$ {\rm{negativep}}\,({\it{y\/}})) \\ 
$\rightarrow$$\;\;\;\;${\rm{negativep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  add-with-carry-of-non-negatives-is-non-negative \\ \index{add-with-carry-of-non-negatives!-is-non-negative}
\=\+({\rm{tcp}}\,({\it{x\/}})\index{tcp} $\wedge$ {\rm{tcp}}\,({\it{y\/}})\index{tcp} $\wedge$ ($\neg$ {\rm{negativep}}\,({\it{x\/}})) $\wedge$ ($\neg$ {\rm{negativep}}\,({\it{y\/}}))) \\ 
$\rightarrow$$\;\;\;\;$($\neg$ {\rm{negativep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}))\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  overflow-lemma1 \\ \index{overflow-lemma1}
\=\+(\=\+{\rm{tcp}}\,({\it{x\/}})\index{tcp} \\ 
$\wedge$$\;\;\;\;${\rm{tcp}}\,({\it{y\/}})\index{tcp} \\ 
$\wedge$$\;\;\;\;${\rm{tc-in-rangep}}\,({\it{x\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$\wedge$$\;\;\;\;${\rm{tc-in-rangep}}\,({\it{y\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$\wedge$$\;\;\;\;${\rm{negativep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}))\- \\ 
$\rightarrow$$\;\;\;\;$($\neg$ {\rm{negativep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, {\rm{exp}}\,({\tt{2}}, {\it{n\/}})\index{exp})\index{add})\index{add})\index{add}))\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  overflow-lemma2 \\ \index{overflow-lemma2}
\=\+(\=\+{\rm{tcp}}\,({\it{x\/}})\index{tcp} \\ 
$\wedge$$\;\;\;\;${\rm{tcp}}\,({\it{y\/}})\index{tcp} \\ 
$\wedge$$\;\;\;\;${\rm{tc-in-rangep}}\,({\it{x\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$\wedge$$\;\;\;\;${\rm{tc-in-rangep}}\,({\it{y\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{negativep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add})))\- \\ 
$\rightarrow$$\;\;\;\;${\rm{negativep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, $-$ {\rm{exp}}\,({\tt{2}}, {\it{n\/}})\index{exp})\index{add})\index{add})\index{add})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  opposite-signs-implies-tc-in-rangep \\ \index{opposite-signs-implies-tc-in-ra!ngep}
\=\+(\=\+{\rm{tcp}}\,({\it{x\/}})\index{tcp} \\ 
$\wedge$$\;\;\;\;${\rm{tcp}}\,({\it{y\/}})\index{tcp} \\ 
$\wedge$$\;\;\;\;${\rm{tc-in-rangep}}\,({\it{x\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$\wedge$$\;\;\;\;${\rm{tc-in-rangep}}\,({\it{y\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$\wedge$$\;\;\;\;${\rm{negativep}}\,({\it{x\/}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{negativep}}\,({\it{y\/}})))\- \\ 
$\rightarrow$$\;\;\;\;${\rm{tc-in-rangep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}, {\it{n\/}})\index{tc-in-rangep}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  opposite-signs-implies-tc-in-rangep-commuted \\ \index{opposite-signs-implies-tc-in-ra!ngep-commuted}
\=\+(\=\+{\rm{tcp}}\,({\it{x\/}})\index{tcp} \\ 
$\wedge$$\;\;\;\;${\rm{tcp}}\,({\it{y\/}})\index{tcp} \\ 
$\wedge$$\;\;\;\;${\rm{tc-in-rangep}}\,({\it{x\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$\wedge$$\;\;\;\;${\rm{tc-in-rangep}}\,({\it{y\/}}, {\it{n\/}})\index{tc-in-rangep} \\ 
$\wedge$$\;\;\;\;${\rm{negativep}}\,({\it{x\/}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{negativep}}\,({\it{y\/}})))\- \\ 
$\rightarrow$$\;\;\;\;${\rm{tc-in-rangep}}\,({\rm{add}}\,({\it{y\/}}, {\rm{add}}\,({\it{x\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}, {\it{n\/}})\index{tc-in-rangep}\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;             Mapping Functions between BV, NAT, and TC                        ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{nat-to-bv} \\  
\=\+{\rm{nat-to-bv}}\,({\it{n\/}}, {\it{size\/}})\index{nat-to-bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{size\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,(\=\+\=\+{\bf if }({\it{n\/}} ${}${\bf{mod}}${}$ {\tt{2}}) $\simeq {\tt{0}}$$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-, \\ 
{\rm{nat-to-bv}}\,({\it{n\/}} $\div$ {\tt{2}}, {\it{size\/}} $-\;1$)\index{nat-to-bv})\-\index{bitv}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-to-nat} \\  
\=\+{\rm{bv-to-nat}}\,({\it{x\/}})\index{bv-to-nat} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{x\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{x\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }\=\+\=\+{\bf if }{\rm{bit}}\,({\it{x\/}})\index{bit}$\;\;${\bf then }{\tt{1}} \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\- \\ 
$+$$\;\;\;\;$({\tt{2}} $*$ {\rm{bv-to-nat}}\,({\rm{vec}}\,({\it{x\/}})\index{vec})\index{bv-to-nat})\-$\;${\bf  endif}\- \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{tc-to-bv} \\  
\=\+{\rm{tc-to-bv}}\,({\it{x\/}}, {\it{size\/}})\index{tc-to-bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{negativep}}\,({\it{x\/}})$\;\;${\bf then }{\rm{incr}}\,({\bf{t}}, {\rm{compl}}\,({\rm{nat-to-bv}}\,({\rm{negative-guts}}\,({\it{x\/}}), {\it{size\/}})\index{nat-to-bv})\index{compl})\index{incr} \\ 
{\bf else }{\rm{nat-to-bv}}\,({\it{x\/}}, {\it{size\/}})\index{nat-to-bv}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-to-tc} \\  
\=\+{\rm{bv-to-tc}}\,({\it{x\/}})\index{bv-to-tc} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitn}}\,({\it{x\/}}, {\rm{size}}\,({\it{x\/}})\index{size})\index{bitn}$\;\;${\bf then }$-$ {\rm{bv-to-nat}}\,({\rm{incr}}\,({\bf{t}}, {\rm{compl}}\,({\it{x\/}})\index{compl})\index{incr})\index{bv-to-nat} \\ 
{\bf else }{\rm{bv-to-nat}}\,({\it{x\/}})\index{bv-to-nat}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{nat-to-tc} \\  
\=\+{\rm{nat-to-tc}}\,({\it{n\/}}, {\it{size\/}})\index{nat-to-tc} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $<$ {\rm{exp}}\,({\tt{2}}, {\it{size\/}} $-\;1$)\index{exp}$\;\;${\bf then }{\it{n\/}} \\ 
{\bf else }$-$ ({\rm{exp}}\,({\tt{2}}, {\it{size\/}})\index{exp} $-$ {\it{n\/}})$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{tc-to-nat} \\  
\=\+{\rm{tc-to-nat}}\,({\it{n\/}}, {\it{size\/}})\index{tc-to-nat} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{negativep}}\,({\it{n\/}})$\;\;${\bf then }{\rm{exp}}\,({\tt{2}}, {\it{size\/}})\index{exp} $-$ {\rm{negative-guts}}\,({\it{n\/}}) \\ 
{\bf else }{\it{n\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                   Elementary Properties of Mapping Functions                 ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Theorem}:  size-of-nat-to-bv \\ \index{size-of-nat-to-bv}
{\rm{size}}\,({\rm{nat-to-bv}}\,({\it{n\/}}, {\it{size\/}})\index{nat-to-bv})\index{size} $=$ {\rm{fix}}\,({\it{size\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-of-tc-to-bv \\ \index{size-of-tc-to-bv}
{\rm{size}}\,({\rm{tc-to-bv}}\,({\it{x\/}}, {\it{size\/}})\index{tc-to-bv})\index{size} $=$ {\rm{fix}}\,({\it{size\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-nat-of-incr \\ \index{bv-to-nat-of-incr}
\=\+{\rm{bv-to-nat}}\,({\rm{incr}}\,({\bf{t}}, {\it{a\/}})\index{incr})\index{bv-to-nat} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{all-onesp}}\,({\it{a\/}})\index{all-onesp}$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }$1\;+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bitn-implies-compl-not-all-onesp \\ \index{bitn-implies-compl-not-all-onesp}
{\rm{bitn}}\,({\it{a\/}}, {\it{i\/}})\index{bitn} $\rightarrow$ ($\neg$ {\rm{all-onesp}}\,({\rm{compl}}\,({\it{a\/}})\index{compl})\index{all-onesp})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  upper-bound-on-bv-to-nat \\ \index{upper-bound-on-bv-to-nat}
{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-nat-of-compl \\ \index{bv-to-nat-of-compl}
{\rm{bv-to-nat}}\,({\rm{compl}}\,({\it{a\/}})\index{compl})\index{bv-to-nat} $=$ (({\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} $-\;1$) $-$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-nat-to-tc-lemma1 \\ \index{bv-to-nat-to-tc-lemma1}
\=\+{\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn} \\ 
$\rightarrow$$\;\;\;\;$({\rm{bv-to-nat}}\,({\rm{incr}}\,({\bf{t}}, {\rm{compl}}\,({\it{a\/}})\index{compl})\index{incr})\index{bv-to-nat} $=$ ({\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} $-$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}))\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-nat-to-tc-lemma2 \\ \index{bv-to-nat-to-tc-lemma2}
\=\+{\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{size}}\,({\it{a\/}})\index{size} $\simeq {\tt{0}}$$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\not<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size} $-\;1$)\index{exp}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-nat-of-trunc \\ \index{bv-to-nat-of-trunc}
{\rm{bv-to-nat}}\,({\rm{trunc}}\,({\it{a\/}}, {\it{n\/}})\index{trunc})\index{bv-to-nat} $=$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} ${}${\bf{mod}}${}$ {\rm{exp}}\,({\tt{2}}, {\it{n\/}})\index{exp})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  all-onesp-of-compl \\ \index{all-onesp-of-compl}
{\rm{all-onesp}}\,({\rm{compl}}\,({\it{a\/}})\index{compl})\index{all-onesp} $=$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $=$ {\tt{0}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tcp-bv-to-tc \\ \index{tcp-bv-to-tc}
{\rm{tcp}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tcp}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  upper-bound-on-non-negative-bv-to-nat \\ \index{upper-bound-on-non-negative-bv-t!o-nat}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) $\wedge$ ($\neg$ {\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn})) \\ 
$\rightarrow$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size} $-\;1$)\index{exp})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  lower-bound-on-negative-bv-to-nat \\ \index{lower-bound-on-negative-bv-to-n!at}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) $\wedge$ {\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn}) \\ 
$\rightarrow$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\not<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size} $-\;1$)\index{exp})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-in-rangep-of-bv-to-tc \\ \index{tc-in-rangep-of-bv-to-tc}
\=\+({\it{n\/}} $=$ {\rm{size}}\,({\it{a\/}})\index{size}) \\ 
$\rightarrow$$\;\;\;\;$({\rm{tc-in-rangep}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\it{n\/}})\index{tc-in-rangep} $=$ ({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})))\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bitn-means-negativep \\ \index{bitn-means-negativep}
({\it{n\/}} $=$ {\rm{size}}\,({\it{a\/}})\index{size}) $\rightarrow$ ({\rm{bitn}}\,({\it{a\/}}, {\it{n\/}})\index{bitn} $=$ {\rm{negativep}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}))
\end{tabbing}


\noindent{\sc Event}:   Disable bitn-means-negativep.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;            Relationship between TC and NAT addition                          ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Theorem}:  plus-to-add \\ \index{plus-to-add}
\=\+({\rm{tcp}}\,({\it{x\/}})\index{tcp} $\wedge$ {\rm{tcp}}\,({\it{y\/}})\index{tcp} $\wedge$ {\rm{tc-in-rangep}}\,({\it{x\/}}, {\it{n\/}})\index{tc-in-rangep} $\wedge$ {\rm{tc-in-rangep}}\,({\it{y\/}}, {\it{n\/}})\index{tc-in-rangep}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{nat-to-tc}}\,(\=\+\=\+({\rm{carry}}\,({\it{c\/}})\index{carry} $+$ {\rm{tc-to-nat}}\,({\it{x\/}}, {\it{n\/}})\index{tc-to-nat} $+$ {\rm{tc-to-nat}}\,({\it{y\/}}, {\it{n\/}})\index{tc-to-nat}) \\ 
${}${\bf{mod}}${}$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\it{n\/}})\index{exp}\-, \\ 
{\it{n\/}})\-\index{nat-to-tc} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{tc-in-rangep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}, {\it{n\/}})\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}) \\ 
{\bf then }{\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, {\rm{exp}}\,({\tt{2}}, {\it{n\/}})\index{exp})\index{add})\index{add})\index{add} \\ 
{\bf else }{\rm{add}}\,({\it{x\/}}, {\rm{add}}\,({\it{y\/}}, {\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, $-$ {\rm{exp}}\,({\tt{2}}, {\it{n\/}})\index{exp})\index{add})\index{add})\index{add}$\;${\bf  endif}\-)\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;      Fundamental Relationships between the Mapping Functions                 ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Theorem}:  bv-to-nat-to-bv \\ \index{bv-to-nat-to-bv}
({\it{size\/}} $=$ {\rm{size}}\,({\it{a\/}})\index{size}) $\rightarrow$ ({\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}, {\it{size\/}})\index{nat-to-bv} $=$ {\rm{fix-bv}}\,({\it{a\/}})\index{fix-bv})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-nat-to-tc \\ \index{bv-to-nat-to-tc}
{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc} $=$ {\rm{nat-to-tc}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-tc}
\end{tabbing}


\noindent{\sc Event}:   Disable bv-to-nat-to-tc.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  nat-to-bv-to-nat \\ \index{nat-to-bv-to-nat}
{\rm{bv-to-nat}}\,({\rm{nat-to-bv}}\,({\it{n\/}}, {\it{size\/}})\index{nat-to-bv})\index{bv-to-nat} $=$ ({\it{n\/}} ${}${\bf{mod}}${}$ {\rm{exp}}\,({\tt{2}}, {\it{size\/}})\index{exp})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-to-bv-to-nat \\ \index{tc-to-bv-to-nat}
\=\+({\rm{tcp}}\,({\it{x\/}})\index{tcp} $\wedge$ {\rm{tc-in-rangep}}\,({\it{x\/}}, {\it{n\/}})\index{tc-in-rangep}) \\ 
$\rightarrow$$\;\;\;\;$({\rm{tc-to-nat}}\,({\it{x\/}}, {\it{n\/}})\index{tc-to-nat} $=$ {\rm{bv-to-nat}}\,({\rm{tc-to-bv}}\,({\it{x\/}}, {\it{n\/}})\index{tc-to-bv})\index{bv-to-nat})\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-to-bv-to-nat.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  bv-to-tc-to-nat \\ \index{bv-to-tc-to-nat}
({\it{n\/}} $=$ {\rm{size}}\,({\it{a\/}})\index{size}) $\rightarrow$ ({\rm{tc-to-nat}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\it{n\/}})\index{tc-to-nat} $=$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat})
\end{tabbing}


\noindent{\sc Event}:   Disable bv-to-tc-to-nat.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  incr-compl-nat-to-bv-0 \\ \index{incr-compl-nat-to-bv-0}
{\rm{incr}}\,({\bf{t}}, {\rm{compl}}\,({\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{x\/}})\index{size})\index{nat-to-bv})\index{compl})\index{incr} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{x\/}})\index{size})\index{nat-to-bv}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bitn-on-implies-non-0 \\ \index{bitn-on-implies-non-0}
{\rm{bitn}}\,({\it{a\/}}, {\it{n\/}})\index{bitn} $\rightarrow$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\not=$ {\tt{0}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-tc-to-bv \\ \index{bv-to-tc-to-bv}
({\it{size\/}} $=$ {\rm{size}}\,({\it{a\/}})\index{size}) $\rightarrow$ ({\rm{tc-to-bv}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\it{size\/}})\index{tc-to-bv} $=$ {\rm{fix-bv}}\,({\it{a\/}})\index{fix-bv})
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                                   Bridge Lemmas                              ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  embed-in-nat-to-bv \\ \index{embed-in-nat-to-bv}
({\it{x\/}} $=$ {\it{y\/}}) $\rightarrow$ ({\rm{nat-to-bv}}\,({\it{x\/}}, {\it{n\/}})\index{nat-to-bv} $=$ {\rm{nat-to-bv}}\,({\it{y\/}}, {\it{n\/}})\index{nat-to-bv})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  embed-in-tc-to-bv \\ \index{embed-in-tc-to-bv}
({\it{x\/}} $=$ {\it{y\/}}) $\rightarrow$ ({\rm{tc-to-bv}}\,({\it{x\/}}, {\it{n\/}})\index{tc-to-bv} $=$ {\rm{tc-to-bv}}\,({\it{y\/}}, {\it{n\/}})\index{tc-to-bv})
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                                   BV-ADDER                                   ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{bv-adder} \\  
\=\+{\rm{bv-adder}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\rm{bitv}}\,({\it{c\/}}, {\sc{btm}}\index{btm})\index{bitv} \\ 
{\bf else }{\rm{bitv}}\,(\=\+{\rm{b-xor}}\,({\it{c\/}}, {\rm{b-xor}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{bit}}\,({\it{b\/}})\index{bit})\index{b-xor})\index{b-xor}, \\ 
{\rm{bv-adder}}\,(\=\+{\rm{b-or}}\,(\=\+{\rm{b-and}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{bit}}\,({\it{b\/}})\index{bit})\index{b-and}, \\ 
{\rm{b-or}}\,(\=\+{\rm{b-and}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\it{c\/}})\index{b-and}, \\ 
{\rm{b-and}}\,({\rm{bit}}\,({\it{b\/}})\index{bit}, {\it{c\/}})\index{b-and})\-\index{b-or})\-\index{b-or}, \\ 
{\rm{vec}}\,({\it{a\/}})\index{vec}, \\ 
{\rm{vec}}\,({\it{b\/}})\index{vec})\-\index{bv-adder})\-\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\rm{bitv}}\,({\it{c\/}}, {\sc{btm}}\index{btm})\index{bitv}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-adder-output} \\  
{\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output} $=$ {\rm{trunc}}\,({\rm{bv-adder}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder}, {\rm{size}}\,({\it{a\/}})\index{size})\index{trunc}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-adder-carry-out} \\  
{\rm{bv-adder-carry-out}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-carry-out} $=$ {\rm{bitn}}\,({\rm{bv-adder}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder}, $1\;+$ {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-adder-overflowp} \\  
\=\+{\rm{bv-adder-overflowp}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-overflowp} \\ 
$=$$\;\;\;\;${\rm{b-and}}\,(\=\+{\rm{b-equv}}\,({\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn}, {\rm{bitn}}\,({\it{b\/}}, {\rm{size}}\,({\it{b\/}})\index{size})\index{bitn})\index{b-equv}, \\ 
{\rm{b-xor}}\,({\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn}, {\rm{bitn}}\,({\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn})\index{b-xor})\-\index{b-and}\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                    Fundamental Properties of BV-ADDER                        ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  size-of-bv-adder \\ \index{size-of-bv-adder}
{\rm{size}}\,({\rm{bv-adder}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder})\index{size} $=$ ($1\;+$ {\rm{size}}\,({\it{a\/}})\index{size})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-nat-of-bv-adder \\ \index{bv-to-nat-of-bv-adder}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-to-nat}}\,({\rm{bv-adder}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder})\index{bv-to-nat} \\ 
$=$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}))\-\-
\end{tabbing}

\begin{verbatim}; From here on we use only the above two lemmas about BV-ADDER
; The definition of BV-ADDER is disabled and henceforth any adder
; with the two properties above would suffice.

\end{verbatim}
\noindent{\sc Event}:   Disable bv-adder.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  bv-adder-non-btm \\ \index{bv-adder-non-btm}
{\rm{bv-adder}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder} $\not=$ {\sc{btm}}\index{btm}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-bv-adder-output \\ \index{size-bv-adder-output}
{\rm{size}}\,({\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                 NAT view of BV-ADDER                                         ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  nat-interpretation-of-bv-adder-output \\ \index{nat-interpretation-of-bv-adder-!output}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-to-nat}}\,({\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output})\index{bv-to-nat} \\ 
$=$$\;\;\;\;$\=\+{\bf if }\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
$<$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\- \\ 
{\bf then }{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry} \\ 
{\bf else }\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
${}${\bf{mod}}${}$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\-$\;${\bf  endif}\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable nat-interpretation-of-bv-adder-output.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  nat-bv-adder-output-seen-as-bit-vector \\ \index{nat-bv-adder-output-seen-as-bit!-vector}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output} \\ 
$=$$\;\;\;\;$\=\+{\bf if }\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
$<$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\- \\ 
{\bf then }{\rm{nat-to-bv}}\,(\=\+{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,(\=\+\=\+(\=\+{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} \\ 
$+$$\;\;\;\;${\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} \\ 
$+$$\;\;\;\;${\rm{carry}}\,({\it{c\/}})\index{carry})\- \\ 
${}${\bf{mod}}${}$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}$\;${\bf  endif}\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable nat-bv-adder-output-seen-as-bit-vector.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  nat-interpretation-of-bv-adder-carry-out \\ \index{nat-interpretation-of-bv-adder-!carry-out}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-carry-out}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-carry-out} \\ 
$=$$\;\;\;\;$(\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
$\not<$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable nat-interpretation-of-bv-adder-carry-out.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                      TC view of BV-ADDER                                     ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-bv-adder-output-lemma1 \\ \index{tc-interpretation-of-bv-adder-o!utput-lemma1}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-to-tc}}\,({\rm{trunc}}\,({\rm{bv-adder}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder}, {\rm{size}}\,({\it{a\/}})\index{size})\index{trunc})\index{bv-to-tc} \\ 
$=$$\;\;\;\;${\rm{nat-to-tc}}\,(\=\+\=\+({\rm{carry}}\,({\it{c\/}})\index{carry} $+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat}) \\ 
${}${\bf{mod}}${}$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-tc})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-bv-adder-output \\ \index{tc-interpretation-of-bv-adder-o!utput}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-to-tc}}\,({\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output})\index{bv-to-tc} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, $-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add})\-\index{add}$\;${\bf  endif}\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-interpretation-of-bv-adder-output-lemma1.

\addvspace{18pt}

\noindent{\sc Event}:   Disable tc-interpretation-of-bv-adder-output.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-bv-adder-output-seen-as-bit-vector-lemma1 \\ \index{tc-bv-adder-output-seen-as-bit-ve!ctor-lemma1}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{tc-to-bv}}\,(\=\+{\rm{bv-to-tc}}\,({\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output})\index{bv-to-tc}, \\ 
{\rm{size}}\,({\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output})\index{size})\-\index{tc-to-bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\-\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, $-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-bv-adder-output-seen-as-bit-vector-lemma1.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-bv-adder-output-seen-as-bit-vector \\ \index{tc-bv-adder-output-seen-as-bit-ve!ctor}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\-\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, $-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-bv-adder-output-seen-as-bit-vector.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-bv-adder-overflowp \\ \index{tc-interpretation-of-bv-adder-ove!rflowp}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-overflowp}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-overflowp} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep}))\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-interpretation-of-bv-adder-overflowp.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;            Definitions and lemmas about subtraction functions                ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


;(defn bv-subtracter (c a b)    ; B - A - C
;  (bv-adder (b-not c) 
;            (bv-not a)
;            b))

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{bv-subtracter-output} \\  
{\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output} $=$ {\rm{bv-adder-output}}\,({\rm{b-not}}\,({\it{c\/}})\index{b-not}, {\rm{bv-not}}\,({\it{a\/}})\index{bv-not}, {\it{b\/}})\index{bv-adder-output}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-subtracter-carry-out} \\  
\=\+{\rm{bv-subtracter-carry-out}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-carry-out} \\ 
$=$$\;\;\;\;${\rm{b-not}}\,({\rm{bv-adder-carry-out}}\,({\rm{b-not}}\,({\it{c\/}})\index{b-not}, {\rm{bv-not}}\,({\it{a\/}})\index{bv-not}, {\it{b\/}})\index{bv-adder-carry-out})\index{b-not}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-subtracter-overflowp} \\  
{\rm{bv-subtracter-overflowp}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-overflowp} $=$ {\rm{bv-adder-overflowp}}\,({\rm{b-not}}\,({\it{c\/}})\index{b-not}, {\rm{bv-not}}\,({\it{a\/}})\index{bv-not}, {\it{b\/}})\index{bv-adder-overflowp}
\end{tabbing}


\begin{tabbing}{\sc Theorem}:  bv-not-is-compl \\ \index{bv-not-is-compl}
{\rm{bv-not}}\,({\it{a\/}})\index{bv-not} $=$ {\rm{compl}}\,({\it{a\/}})\index{compl}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  subtract-lemma1 \\ \index{subtract-lemma1}
\=\+({\rm{size}}\,({\it{b\/}})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}) \\ 
$\rightarrow$$\;\;\;\;$((({\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $-$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}) $<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}) $=$ {\bf{t}})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  subtract-lemma2 \\ \index{subtract-lemma2}
(({\it{b\/}} $\not\simeq {\tt{0}}$) $\wedge$ (({\it{b\/}} $-\;1$) $\not<$ {\it{a\/}})) $\rightarrow$ ((({\it{b\/}} $+$ (({\it{n\/}} $-\;1$) $-$ {\it{a\/}})) $<$ {\it{n\/}}) $=$ {\bf{f}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  subtract-lemma3 \\ \index{subtract-lemma3}
\=\+(({\it{b\/}} $\not\simeq {\tt{0}}$) $\wedge$ (({\it{b\/}} $-\;1$) $\not<$ {\it{a\/}}) $\wedge$ ({\it{a\/}} $<$ {\it{n\/}})) \\ 
$\rightarrow$$\;\;\;\;$((({\it{b\/}} $+$ (({\it{n\/}} $-\;1$) $-$ {\it{a\/}})) $-$ {\it{n\/}}) $=$ (({\it{b\/}} $-\;1$) $-$ {\it{a\/}}))\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  subtract-lemma4 \\ \index{subtract-lemma4}
\=\+({\rm{size}}\,({\it{b\/}})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}) \\ 
$\rightarrow$$\;\;\;\;$(((({\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $-\;1$) $-$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}) $<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}) $=$ {\bf{t}})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-bv-subtracter-output \\ \index{size-bv-subtracter-output}
{\rm{size}}\,({\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                 NAT view of BV-SUBTRACTER                                    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  nat-interpretation-of-bv-subtracter-output \\ \index{nat-interpretation-of-bv-subtra!cter-output}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-to-nat}}\,({\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output})\index{bv-to-nat} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $\not<$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
{\bf then }{\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $-$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
{\bf else }\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} \\ 
$-$$\;\;\;\;$(\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
$-$$\;\;\;\;${\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat})\-\-$\;${\bf  endif}\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable nat-interpretation-of-bv-subtracter-output.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  nat-bv-subtracter-output-seen-as-bit-vector \\ \index{nat-bv-subtracter-output-seen-a!s-bit-vector}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $\not<$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
{\bf then }{\rm{nat-to-bv}}\,(\=\+{\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $-$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}), \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,(\=\+\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} \\ 
$-$$\;\;\;\;$(\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
$-$$\;\;\;\;${\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat})\-\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}$\;${\bf  endif}\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable nat-bv-subtracter-output-seen-as-bit-vector.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  equal-lessp-hack \\ \index{equal-lessp-hack}
\=\+(({\it{x\/}} $<$ {\it{y\/}}) $=$ {\it{z\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} $<$ {\it{y\/}}$\;\;${\bf then }{\it{z\/}} $=$ {\bf{t}} \\ 
{\bf else }{\it{z\/}} $=$ {\bf{f}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  nat-interpretation-of-bv-subtracter-carry-out \\ \index{nat-interpretation-of-bv-subtra!cter-carry-out}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-subtracter-carry-out}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-carry-out} \\ 
$=$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $<$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry})))\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable nat-interpretation-of-bv-subtracter-carry-out.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                      TC view of BV-SUBTRACTER                                ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{tc-minus} \\  
\=\+{\rm{tc-minus}}\,({\it{x\/}})\index{tc-minus} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{negativep}}\,({\it{x\/}})$\;\;${\bf then }{\rm{negative-guts}}\,({\it{x\/}}) \\ 
{\bf elseif }{\it{x\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }$-$ {\it{x\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-minus-add \\ \index{tc-minus-add}
{\rm{tc-minus}}\,({\rm{add}}\,({\it{x\/}}, {\it{y\/}})\index{add})\index{tc-minus} $=$ {\rm{add}}\,({\rm{tc-minus}}\,({\it{x\/}})\index{tc-minus}, {\rm{tc-minus}}\,({\it{y\/}})\index{tc-minus})\index{add}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bitn-compl \\ \index{bitn-compl}
(({\it{n\/}} $\not\simeq {\tt{0}}$) $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $\not<$ {\it{n\/}})) $\rightarrow$ ({\rm{bitn}}\,({\rm{compl}}\,({\it{a\/}})\index{compl}, {\it{n\/}})\index{bitn} $=$ ($\neg$ {\rm{bitn}}\,({\it{a\/}}, {\it{n\/}})\index{bitn}))
\end{tabbing}

\begin{verbatim};(prove-lemma bitn-on-implies-non-0 (rewrite)
;  (implies (bitn a n) (not (equal (bv-to-nat a) 0))))

\end{verbatim}\begin{tabbing}{\sc Theorem}:  equal-difference-0 \\ \index{equal-difference-0}
(({\it{x\/}} $-$ {\it{y\/}}) $=$ {\tt{0}}) $=$ ({\it{y\/}} $\not<$ {\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  top-bit-off-implies-smaller \\ \index{top-bit-off-implies-smaller}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) $\wedge$ ($\neg$ {\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn})) \\ 
$\rightarrow$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $<$ ({\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} $-\;1$))\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-minus-bv-to-tc \\ \index{tc-minus-bv-to-tc}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc} $=$ {\tt{0}}$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }{\rm{add}}\,({\tt{1}}, {\rm{bv-to-tc}}\,({\rm{compl}}\,({\it{a\/}})\index{compl})\index{bv-to-tc})\index{add}$\;${\bf  endif}\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{tc-fix} \\  
\=\+{\rm{tc-fix}}\,({\it{x\/}})\index{tc-fix} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{tcp}}\,({\it{x\/}})\index{tcp}$\;\;${\bf then }{\it{x\/}} \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tcp-add \\ \index{tcp-add}
({\rm{tcp}}\,({\it{x\/}})\index{tcp} $\rightarrow$ {\rm{tcp}}\,({\rm{add}}\,({\it{x\/}}, {\it{y\/}})\index{add})\index{tcp}) $\wedge$ ({\rm{tcp}}\,({\it{y\/}})\index{tcp} $\rightarrow$ {\rm{tcp}}\,({\rm{add}}\,({\it{x\/}}, {\it{y\/}})\index{add})\index{tcp})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  add-0 \\ \index{add-0}
{\rm{add}}\,({\tt{0}}, {\it{x\/}})\index{add} $=$ {\rm{tc-fix}}\,({\it{x\/}})\index{tc-fix}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  add-1-1 \\ \index{add-1-1}
{\rm{add}}\,({\tt{1}}, {\rm{add}}\,({\tt{-1}}, {\it{x\/}})\index{add})\index{add} $=$ {\rm{tc-fix}}\,({\it{x\/}})\index{tc-fix}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-tc-compl-0 \\ \index{bv-to-tc-compl-0}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) $\wedge$ ({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc} $=$ {\tt{0}})) \\ 
$\rightarrow$$\;\;\;\;$({\rm{bv-to-tc}}\,({\rm{compl}}\,({\it{a\/}})\index{compl})\index{bv-to-tc} $=$ {\tt{-1}})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-minus-add-carry \\ \index{tc-minus-add-carry}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus} \\ 
$=$$\;\;\;\;${\rm{add}}\,({\rm{bv-to-tc}}\,({\rm{compl}}\,({\it{a\/}})\index{compl})\index{bv-to-tc}, {\rm{carry}}\,($\neg$ {\it{c\/}})\index{carry})\index{add})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  boolp-b-not \\ \index{boolp-b-not}
{\rm{boolp}}\,({\rm{b-not}}\,({\it{x\/}})\index{b-not})\index{boolp}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  compl-not-btm \\ \index{compl-not-btm}
({\rm{compl}}\,({\it{a\/}})\index{compl} $=$ {\sc{btm}}\index{btm}) $=$ (($\neg$ {\rm{bitvp}}\,({\it{a\/}})\index{bitvp}) $\vee$ ({\it{a\/}} $=$ {\sc{btm}}\index{btm}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-bv-subtracter-output \\ \index{tc-interpretation-of-bv-subtracte!r-output}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-to-tc}}\,({\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output})\index{bv-to-tc} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add})\-\index{add}$\;${\bf  endif}\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-interpretation-of-bv-subtracter-output.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  tc-bv-subtracter-output-seen-as-bit-vector-lemma1 \\ \index{tc-bv-subtracter-output-seen-as!-bit-vector-lemma1}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{tc-to-bv}}\,(\=\+{\rm{bv-to-tc}}\,({\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output})\index{bv-to-tc}, \\ 
{\rm{size}}\,({\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output})\index{size})\-\index{tc-to-bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{carry}}\,({\it{c\/}})\index{carry})\-\index{add})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{carry}}\,({\it{c\/}})\index{carry})\-\index{add})\index{tc-minus})\-\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-bv-subtracter-output-seen-as-bit-vector-lemma1.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-bv-subtracter-output-seen-as-bit-vector \\ \index{tc-bv-subtracter-output-seen-as!-bit-vector}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{tc-to-bv}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add}) \\ 
{\bf then }{\rm{tc-to-bv}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv} \\ 
{\bf else }{\rm{tc-to-bv}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv}$\;${\bf  endif}\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-bv-subtracter-output-seen-as-bit-vector.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-bv-subtracter-overflowp \\ \index{tc-interpretation-of-bv-subtracte!r-overflowp}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-subtracter-overflowp}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-overflowp} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep}))\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-interpretation-of-bv-subtracter-overflowp.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;            Definitions and lemmas for shift and rotate functions             ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{v-append} \\  
\=\+{\rm{v-append}}\,({\it{a\/}}, {\it{b\/}})\index{v-append} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\it{b\/}} \\ 
{\bf else }{\rm{bitv}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{v-append}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\it{b\/}})\index{v-append})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\it{b\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-lsr} \\  
\=\+{\rm{v-lsr}}\,({\it{a\/}})\index{v-lsr} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{v-append}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{bitv}}\,({\bf{f}}, {\sc{btm}}\index{btm})\index{bitv})\index{v-append}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-lsl} \\  
\=\+{\rm{v-lsl}}\,({\it{a\/}})\index{v-lsl} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{v-append}}\,({\rm{bitv}}\,({\bf{f}}, {\sc{btm}}\index{btm})\index{bitv}, {\rm{trunc}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size} $-\;1$)\index{trunc})\index{v-append}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-asr} \\  
\=\+{\rm{v-asr}}\,({\it{a\/}})\index{v-asr} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{v-append}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{bitv}}\,({\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn}, {\sc{btm}}\index{btm})\index{bitv})\index{v-append}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-asl}$\;\;$
{\rm{v-asl}}\,({\it{a\/}})\index{v-asl} $=$ {\rm{v-lsl}}\,({\it{a\/}})\index{v-lsl}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-ror} \\  
\=\+{\rm{v-ror}}\,({\it{a\/}}, {\it{c\/}})\index{v-ror} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{v-append}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{bitv}}\,({\it{c\/}}, {\sc{btm}}\index{btm})\index{bitv})\index{v-append}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-rol} \\  
\=\+{\rm{v-rol}}\,({\it{a\/}}, {\it{c\/}})\index{v-rol} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{v-append}}\,({\rm{bitv}}\,({\it{c\/}}, {\sc{btm}}\index{btm})\index{bitv}, {\rm{trunc}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size} $-\;1$)\index{trunc})\index{v-append}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-append}$\;\;$
{\rm{bv-append}}\,({\it{a\/}}, {\it{b\/}})\index{bv-append} $=$ {\rm{v-append}}\,({\it{a\/}}, {\it{b\/}})\index{v-append}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-lsr}$\;\;$
{\rm{bv-lsr}}\,({\it{a\/}})\index{bv-lsr} $=$ {\rm{v-lsr}}\,({\it{a\/}})\index{v-lsr}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-asr}$\;\;$
{\rm{bv-asr}}\,({\it{a\/}})\index{bv-asr} $=$ {\rm{v-asr}}\,({\it{a\/}})\index{v-asr}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-ror}$\;\;$
{\rm{bv-ror}}\,({\it{a\/}}, {\it{c\/}})\index{bv-ror} $=$ {\rm{v-ror}}\,({\it{a\/}}, {\it{c\/}})\index{v-ror}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;            Natural and two's complement interpretation of shifters           ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  bv-to-nat-v-append \\ \index{bv-to-nat-v-append}
\=\+{\rm{bv-to-nat}}\,({\rm{v-append}}\,({\it{a\/}}, {\it{b\/}})\index{v-append})\index{bv-to-nat} \\ 
$=$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ ({\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $*$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}))\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-lsr-divides-by-two-lemma \\ \index{bv-lsr-divides-by-two-lemma}
{\rm{v-lsr}}\,({\it{a\/}})\index{v-lsr} $=$ {\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\div$ {\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{mod2} \\  
\=\+{\rm{mod2}}\,({\it{x\/}})\index{mod2} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{negativep}}\,({\it{x\/}})$\;\;${\bf then }$-$ (($1\;+$ {\rm{negative-guts}}\,({\it{x\/}})) $\div$ {\tt{2}}) \\ 
{\bf else }{\it{x\/}} $\div$ {\tt{2}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bitvp-v-append \\ \index{bitvp-v-append}
\=\+{\rm{bitvp}}\,({\rm{v-append}}\,({\it{a\/}}, {\it{b\/}})\index{v-append})\index{bitvp} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp}$\;\;${\bf then }({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) $\vee$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
{\bf else }{\rm{bitvp}}\,({\it{b\/}})\index{bitvp}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bitn-v-append \\ \index{bitn-v-append}
\=\+{\rm{bitn}}\,({\rm{v-append}}\,({\it{a\/}}, {\it{b\/}})\index{v-append}, {\it{n\/}})\index{bitn} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{size}}\,({\it{a\/}})\index{size} $<$ {\it{n\/}}$\;\;${\bf then }{\rm{bitn}}\,({\it{b\/}}, {\it{n\/}} $-$ {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn} \\ 
{\bf else }{\rm{bitn}}\,({\it{a\/}}, {\it{n\/}})\index{bitn}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-append \\ \index{size-v-append}
{\rm{size}}\,({\rm{v-append}}\,({\it{a\/}}, {\it{b\/}})\index{v-append})\index{size} $=$ ({\rm{size}}\,({\it{a\/}})\index{size} $+$ {\rm{size}}\,({\it{b\/}})\index{size})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-x-x-1 \\ \index{difference-x-x-1}
\=\+({\it{x\/}} $-$ ({\it{x\/}} $-\;1$)) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }{\tt{1}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-nat-of-twos-compl \\ \index{bv-to-nat-of-twos-compl}
\=\+{\rm{bv-to-nat}}\,({\rm{incr}}\,({\bf{t}}, {\rm{compl}}\,({\it{a\/}})\index{compl})\index{incr})\index{bv-to-nat} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $=$ {\tt{0}}$\;\;${\bf then }{\tt{0}} \\ 
{\bf else }{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} $-$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  difference-2x-x \\ \index{difference-2x-x}
(({\tt{2}} $*$ {\it{y\/}}) $-$ ({\it{x\/}} $+$ {\it{y\/}})) $=$ ({\it{y\/}} $-$ {\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  quotient-crock1 \\ \index{quotient-crock1}
(($1\;+$ (({\tt{2}} $*$ {\it{y\/}}) $-$ ({\tt{2}} $*$ {\it{x\/}}))) $\div$ {\tt{2}}) $=$ ({\it{y\/}} $-$ {\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  add1-difference-sub1 \\ \index{add1-difference-sub1}
\=\+($1\;+$ (({\it{x\/}} $-\;1$) $-$ {\it{y\/}})) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{y\/}} $<$ {\it{x\/}}$\;\;${\bf then }{\it{x\/}} $-$ {\it{y\/}} \\ 
{\bf else }{\tt{1}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  quotient-crock2 \\ \index{quotient-crock2}
((({\tt{2}} $*$ {\it{y\/}}) $-$ ({\tt{2}} $*$ {\it{x\/}})) $\div$ {\tt{2}}) $=$ ({\it{y\/}} $-$ {\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-asr-divides-by-two \\ \index{bv-asr-divides-by-two}
{\rm{bv-to-tc}}\,({\rm{bv-asr}}\,({\it{a\/}})\index{bv-asr})\index{bv-to-tc} $=$ {\rm{mod2}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{mod2}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;            Definitions and lemmas about hardware if                          ;;
;;            and constructor for ALU result                                    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-if} \\  
{\rm{b-if}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{b-if} $=$ {\rm{b-nand}}\,({\rm{b-nand}}\,({\it{c\/}}, {\it{a\/}})\index{b-nand}, {\rm{b-nand}}\,({\rm{b-not}}\,({\it{c\/}})\index{b-not}, {\it{b\/}})\index{b-nand})\index{b-nand}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-if} \\  
\=\+{\rm{bv-if}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-if} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\rm{b-if}}\,({\it{c\/}}, {\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{bit}}\,({\it{b\/}})\index{bit})\index{b-if}, {\rm{bv-if}}\,({\it{c\/}}, {\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{vec}}\,({\it{b\/}})\index{vec})\index{bv-if})\index{bitv}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-if-works \\ \index{bv-if-works}
\=\+{\rm{bv-if}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-if} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{c\/}} \\ 
{\bf then }\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp}$\;\;${\bf then }{\it{a\/}} \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\- \\ 
{\bf else }{\rm{trunc}}\,({\it{b\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{trunc}$\;${\bf  endif}\-\-
\end{tabbing}


\noindent{\sc Event}:   Add the shell {\it{bv-cv\/}}\index{bv-cv}, with recognizer function symbol {\it{bv-cvp\/}} and 3 accessors: {\it{bv\/}}, with type restriction (one-of bitvp) and default value btm; {\it{c\/}}, with type restriction (one-of truep falsep) and default value false; {\it{v\/}}, with type restriction (one-of truep falsep) and default value false.

\addvspace{18pt}

\begin{tabbing}{\sc Definition}:\index{bv-cv-if} \\  
\=\+{\rm{bv-cv-if}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-cv-if} \\ 
$=$$\;\;\;\;${\rm{bv-cv}}\,({\rm{bv-if}}\,({\it{c\/}}, {\rm{bv}}\,({\it{a\/}})\index{bv}, {\rm{bv}}\,({\it{b\/}})\index{bv})\index{bv-if}, {\rm{b-if}}\,({\it{c\/}}, {\rm{c}}\,({\it{a\/}})\index{c}, {\rm{c}}\,({\it{b\/}})\index{c})\index{b-if}, {\rm{b-if}}\,({\it{c\/}}, {\rm{v}}\,({\it{a\/}})\index{v}, {\rm{v}}\,({\it{b\/}})\index{v})\index{b-if})\index{bv-cv}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  trunc-size \\ \index{trunc-size}
({\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{b\/}})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size})) $\rightarrow$ ({\rm{trunc}}\,({\it{b\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{trunc} $=$ {\it{b\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-cv-if-works \\ \index{bv-cv-if-works}
\=\+({\rm{bv-cvp}}\,({\it{a\/}})\index{bv-cvp} $\wedge$ {\rm{bv-cvp}}\,({\it{b\/}})\index{bv-cvp} $\wedge$ ({\rm{size}}\,({\rm{bv}}\,({\it{a\/}})\index{bv})\index{size} $=$ {\rm{size}}\,({\rm{bv}}\,({\it{b\/}})\index{bv})\index{size})) \\ 
$\rightarrow$$\;\;\;\;$(({\rm{bv-cv-if}}\,({\bf{t}}, {\it{a\/}}, {\it{b\/}})\index{bv-cv-if} $=$ {\it{a\/}}) $\wedge$ ({\rm{bv-cv-if}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-cv-if} $=$ {\it{b\/}}))\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;            SIZE lemmas                                                       ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  size-bv-bv-cv-if \\ \index{size-bv-bv-cv-if}
{\rm{size}}\,({\rm{bv}}\,({\rm{bv-cv-if}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-cv-if})\index{bv})\index{size} $=$ {\rm{size}}\,({\rm{bv}}\,({\it{a\/}})\index{bv})\index{size}
\end{tabbing}

\begin{verbatim}; We rewrite "bv-not" to "v-not", etc., and so we need these size lemmas about
; the v-functions.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  size-v-not \\ \index{size-v-not}
{\rm{size}}\,({\rm{v-not}}\,({\it{a\/}})\index{v-not})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-and \\ \index{size-v-and}
{\rm{size}}\,({\rm{v-and}}\,({\it{a\/}}, {\it{b\/}})\index{v-and})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-or \\ \index{size-v-or}
{\rm{size}}\,({\rm{v-or}}\,({\it{a\/}}, {\it{b\/}})\index{v-or})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-xor \\ \index{size-v-xor}
{\rm{size}}\,({\rm{v-xor}}\,({\it{a\/}}, {\it{b\/}})\index{v-xor})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-append-1 \\ \index{size-v-append-1}
\=\+{\rm{size}}\,(\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{v-append}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{bitv}}\,({\it{x\/}}, {\sc{btm}}\index{btm})\index{bitv})\index{v-append}$\;${\bf  endif}\- \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-)\index{size} \\ 
$=$$\;\;\;\;${\rm{size}}\,({\it{a\/}})\index{size}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-append-2 \\ \index{size-v-append-2}
\=\+{\rm{size}}\,({\rm{v-append}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{bitv}}\,({\it{x\/}}, {\sc{btm}}\index{btm})\index{bitv})\index{v-append})\index{size} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\tt{1}} \\ 
{\bf else }{\rm{size}}\,({\it{a\/}})\index{size}$\;${\bf  endif}\- \\ 
{\bf else }{\tt{1}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};  We have already proved (SIZE (BV-ADDER-OUTPUT C A B)) = (SIZE A) and
;                         (SIZE (BV-SUBTRACTER-OUTPUT C A B)) = (SIZE A).
\end{verbatim}
\newpage
\begin{verbatim}

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;            ALU definition                                                    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}
\noindent{\sc Event}:   Disable bv-cv-if.

\addvspace{18pt}

\begin{tabbing}{\sc Definition}:\index{bv-alu-cv} \\  
\=\+{\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\it{op-code\/}})\index{bv-alu-cv} \\ 
$=$$\;\;\;\;${\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{4}})\index{bitn}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{3}})\index{bitn}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{2}})\index{bitn}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}, \\ 
{\rm{bv-cv}}\,({\it{a\/}}, {\bf{f}}, {\bf{f}})\index{bv-cv}, \\ 
{\rm{bv-cv}}\,({\rm{bv-not}}\,({\it{a\/}})\index{bv-not}, {\bf{f}}, {\bf{f}})\index{bv-cv})\-\index{bv-cv-if}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}, \\ 
{\rm{bv-cv}}\,({\rm{bv-and}}\,({\it{a\/}}, {\it{b\/}})\index{bv-and}, {\bf{f}}, {\bf{f}})\index{bv-cv}, \\ 
{\rm{bv-cv}}\,({\rm{bv-or}}\,({\it{a\/}}, {\it{b\/}})\index{bv-or}, {\bf{f}}, {\bf{f}})\index{bv-cv})\-\index{bv-cv-if})\-\index{bv-cv-if}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{2}})\index{bitn}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}, \\ 
{\rm{bv-cv}}\,({\rm{bv-xor}}\,({\it{a\/}}, {\it{b\/}})\index{bv-xor}, {\bf{f}}, {\bf{f}})\index{bv-cv}, \\ 
{\rm{bv-cv}}\,({\rm{bv-lsr}}\,({\it{a\/}})\index{bv-lsr}, {\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}, {\bf{f}})\index{bv-cv})\-\index{bv-cv-if}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}, \\ 
{\rm{bv-cv}}\,({\rm{bv-asr}}\,({\it{a\/}})\index{bv-asr}, {\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}, {\bf{f}})\index{bv-cv}, \\ 
{\rm{bv-cv}}\,(\=\+{\rm{bv-ror}}\,({\it{a\/}}, {\it{c\/}})\index{bv-ror}, \\ 
\=\+{\bf if }{\rm{size}}\,({\it{a\/}})\index{size} $\simeq {\tt{0}}$$\;\;${\bf then }{\it{c\/}} \\ 
{\bf else }{\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}$\;${\bf  endif}\-, \\ 
{\bf{f}})\-\index{bv-cv})\-\index{bv-cv-if})\-\index{bv-cv-if})\-\index{bv-cv-if}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{3}})\index{bitn}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{2}})\index{bitn}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}, \\ 
{\rm{bv-cv}}\,(\=\+{\rm{bv-subtracter-output}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output}, \\ 
{\rm{bv-subtracter-carry-out}}\,(\=\+{\bf{f}}, \\ 
{\it{a\/}}, \\ 
{\it{b\/}})\-\index{bv-subtracter-carry-out}, \\ 
{\rm{bv-subtracter-overflowp}}\,(\=\+{\bf{f}}, \\ 
{\it{a\/}}, \\ 
{\it{b\/}})\-\index{bv-subtracter-overflowp})\-\index{bv-cv}, \\ 
{\rm{bv-cv}}\,(\=\+{\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output}, \\ 
{\rm{bv-subtracter-carry-out}}\,(\=\+{\it{c\/}}, \\ 
{\it{a\/}}, \\ 
{\it{b\/}})\-\index{bv-subtracter-carry-out}, \\ 
{\rm{bv-subtracter-overflowp}}\,(\=\+{\it{c\/}}, \\ 
{\it{a\/}}, \\ 
{\it{b\/}})\-\index{bv-subtracter-overflowp})\-\index{bv-cv})\-\index{bv-cv-if}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}, \\ 
{\rm{bv-cv}}\,(\=\+{\rm{bv-subtracter-output}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}, \\ 
{\it{a\/}})\-\index{bv-subtracter-output}, \\ 
{\rm{bv-subtracter-carry-out}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}, \\ 
{\it{a\/}})\-\index{bv-subtracter-carry-out}, \\ 
{\rm{bv-subtracter-overflowp}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}, \\ 
{\it{a\/}})\-\index{bv-subtracter-overflowp})\-\index{bv-cv}, \\ 
{\rm{bv-cv}}\,(\=\+{\rm{bv-subtracter-output}}\,(\=\+{\bf{f}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-subtracter-output}, \\ 
{\rm{bv-subtracter-carry-out}}\,(\=\+{\bf{f}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-subtracter-carry-out}, \\ 
{\rm{bv-subtracter-overflowp}}\,(\=\+{\bf{f}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-subtracter-overflowp})\-\index{bv-cv})\-\index{bv-cv-if})\-\index{bv-cv-if}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{2}})\index{bitn}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}, \\ 
{\rm{bv-cv}}\,(\=\+{\rm{bv-adder-output}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output}, \\ 
{\rm{bv-adder-carry-out}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-carry-out}, \\ 
{\rm{bv-adder-overflowp}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-overflowp})\-\index{bv-cv}, \\ 
{\rm{bv-cv}}\,(\=\+{\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output}, \\ 
{\rm{bv-adder-carry-out}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-carry-out}, \\ 
{\rm{bv-adder-overflowp}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-overflowp})\-\index{bv-cv})\-\index{bv-cv-if}, \\ 
{\rm{bv-cv-if}}\,(\=\+{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}, \\ 
{\rm{bv-cv}}\,(\=\+{\rm{bv-adder-output}}\,(\=\+{\bf{t}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-adder-output}, \\ 
{\rm{bv-adder-carry-out}}\,(\=\+{\bf{t}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-adder-carry-out}, \\ 
{\rm{bv-adder-overflowp}}\,(\=\+{\bf{t}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-adder-overflowp})\-\index{bv-cv}, \\ 
{\rm{bv-cv}}\,({\it{a\/}}, {\bf{f}}, {\bf{f}})\index{bv-cv})\-\index{bv-cv-if})\-\index{bv-cv-if})\-\index{bv-cv-if})\-\index{bv-cv-if}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  v-not-is-compl \\ \index{v-not-is-compl}
{\rm{v-not}}\,({\it{a\/}})\index{v-not} $=$ {\rm{compl}}\,({\it{a\/}})\index{compl}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-and-is-v-and \\ \index{bv-and-is-v-and}
{\rm{bv-and}}\,({\it{a\/}}, {\it{b\/}})\index{bv-and} $=$ {\rm{v-and}}\,({\it{a\/}}, {\it{b\/}})\index{v-and}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-or-is-v-or \\ \index{bv-or-is-v-or}
{\rm{bv-or}}\,({\it{a\/}}, {\it{b\/}})\index{bv-or} $=$ {\rm{v-or}}\,({\it{a\/}}, {\it{b\/}})\index{v-or}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-xor-is-v-xor \\ \index{bv-xor-is-v-xor}
{\rm{bv-xor}}\,({\it{a\/}}, {\it{b\/}})\index{bv-xor} $=$ {\rm{v-xor}}\,({\it{a\/}}, {\it{b\/}})\index{v-xor}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-cv-if-reduce \\ \index{bv-cv-if-reduce}
{\rm{bv-cv-if}}\,({\it{c\/}}, {\rm{bv-cv}}\,({\it{x\/}}, {\it{y\/}}, {\it{z\/}})\index{bv-cv}, {\rm{bv-cv}}\,({\it{x\/}}, {\it{y\/}}, {\it{z\/}})\index{bv-cv})\index{bv-cv-if} $=$ {\rm{bv-cv}}\,({\it{x\/}}, {\it{y\/}}, {\it{z\/}})\index{bv-cv}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;           BV-ALU with theorem-prover "ifs".  This was done to speed the      ;;
;;           rewriting when proving the large lemmas that follow.               ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  bv-alu-cv-with-ifs \\ \index{bv-alu-cv-with-ifs}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\it{op-code\/}})\index{bv-alu-cv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{4}})\index{bitn} \\ 
{\bf then }\=\+{\bf if }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{3}})\index{bitn} \\ 
{\bf then }\=\+{\bf if }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{2}})\index{bitn} \\ 
{\bf then }\=\+{\bf if }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}$\;\;${\bf then }{\rm{bv-cv}}\,({\it{a\/}}, {\bf{f}}, {\bf{f}})\index{bv-cv} \\ 
{\bf else }{\rm{bv-cv}}\,({\rm{bv-not}}\,({\it{a\/}})\index{bv-not}, {\bf{f}}, {\bf{f}})\index{bv-cv}$\;${\bf  endif}\- \\ 
{\bf elseif }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}$\;\;${\bf then }{\rm{bv-cv}}\,({\rm{bv-and}}\,({\it{a\/}}, {\it{b\/}})\index{bv-and}, {\bf{f}}, {\bf{f}})\index{bv-cv} \\ 
{\bf else }{\rm{bv-cv}}\,({\rm{bv-or}}\,({\it{a\/}}, {\it{b\/}})\index{bv-or}, {\bf{f}}, {\bf{f}})\index{bv-cv}$\;${\bf  endif}\- \\ 
{\bf elseif }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{2}})\index{bitn} \\ 
{\bf then }\=\+{\bf if }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn}$\;\;${\bf then }{\rm{bv-cv}}\,({\rm{bv-xor}}\,({\it{a\/}}, {\it{b\/}})\index{bv-xor}, {\bf{f}}, {\bf{f}})\index{bv-cv} \\ 
{\bf else }{\rm{bv-cv}}\,({\rm{bv-lsr}}\,({\it{a\/}})\index{bv-lsr}, {\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}, {\bf{f}})\index{bv-cv}$\;${\bf  endif}\- \\ 
{\bf elseif }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn} \\ 
{\bf then }{\rm{bv-cv}}\,({\rm{bv-asr}}\,({\it{a\/}})\index{bv-asr}, {\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}, {\bf{f}})\index{bv-cv} \\ 
{\bf else }{\rm{bv-cv}}\,(\=\+{\rm{bv-ror}}\,({\it{a\/}}, {\it{c\/}})\index{bv-ror}, \\ 
\=\+{\bf if }{\rm{size}}\,({\it{a\/}})\index{size} $\simeq {\tt{0}}$$\;\;${\bf then }{\it{c\/}} \\ 
{\bf else }{\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}$\;${\bf  endif}\-, \\ 
{\bf{f}})\-\index{bv-cv}$\;${\bf  endif}\- \\ 
{\bf elseif }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{3}})\index{bitn} \\ 
{\bf then }\=\+{\bf if }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{2}})\index{bitn} \\ 
{\bf then }\=\+{\bf if }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn} \\ 
{\bf then }{\rm{bv-cv}}\,(\=\+{\rm{bv-subtracter-output}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output}, \\ 
{\rm{bv-subtracter-carry-out}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-carry-out}, \\ 
{\rm{bv-subtracter-overflowp}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-overflowp})\-\index{bv-cv} \\ 
{\bf else }{\rm{bv-cv}}\,(\=\+{\rm{bv-subtracter-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-output}, \\ 
{\rm{bv-subtracter-carry-out}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-carry-out}, \\ 
{\rm{bv-subtracter-overflowp}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-subtracter-overflowp})\-\index{bv-cv}$\;${\bf  endif}\- \\ 
{\bf elseif }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn} \\ 
{\bf then }{\rm{bv-cv}}\,(\=\+{\rm{bv-subtracter-output}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}, \\ 
{\it{a\/}})\-\index{bv-subtracter-output}, \\ 
{\rm{bv-subtracter-carry-out}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}, \\ 
{\it{a\/}})\-\index{bv-subtracter-carry-out}, \\ 
{\rm{bv-subtracter-overflowp}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}, \\ 
{\it{a\/}})\-\index{bv-subtracter-overflowp})\-\index{bv-cv} \\ 
{\bf else }{\rm{bv-cv}}\,(\=\+{\rm{bv-subtracter-output}}\,(\=\+{\bf{f}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-subtracter-output}, \\ 
{\rm{bv-subtracter-carry-out}}\,(\=\+{\bf{f}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-subtracter-carry-out}, \\ 
{\rm{bv-subtracter-overflowp}}\,(\=\+{\bf{f}}, \\ 
{\it{a\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\index{bv-subtracter-overflowp})\-\index{bv-cv}$\;${\bf  endif}\- \\ 
{\bf elseif }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{2}})\index{bitn} \\ 
{\bf then }\=\+{\bf if }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn} \\ 
{\bf then }{\rm{bv-cv}}\,(\=\+{\rm{bv-adder-output}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output}, \\ 
{\rm{bv-adder-carry-out}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-carry-out}, \\ 
{\rm{bv-adder-overflowp}}\,({\bf{f}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-overflowp})\-\index{bv-cv} \\ 
{\bf else }{\rm{bv-cv}}\,(\=\+{\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-output}, \\ 
{\rm{bv-adder-carry-out}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-carry-out}, \\ 
{\rm{bv-adder-overflowp}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{bv-adder-overflowp})\-\index{bv-cv}$\;${\bf  endif}\- \\ 
{\bf elseif }{\rm{bitn}}\,({\it{op-code\/}}, {\tt{1}})\index{bitn} \\ 
{\bf then }{\rm{bv-cv}}\,(\=\+{\rm{bv-adder-output}}\,({\bf{t}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-adder-output}, \\ 
{\rm{bv-adder-carry-out}}\,({\bf{t}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-adder-carry-out}, \\ 
{\rm{bv-adder-overflowp}}\,({\bf{t}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-adder-overflowp})\-\index{bv-cv} \\ 
{\bf else }{\rm{bv-cv}}\,({\it{a\/}}, {\bf{f}}, {\bf{f}})\index{bv-cv}$\;${\bf  endif}\-)\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;           Boolean ALU help lemmas                                            ;;
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\end{verbatim}\begin{tabbing}{\sc Theorem}:  nat-to-bv-of-2i \\ \index{nat-to-bv-of-2i}
\=\+{\rm{boolp}}\,({\it{c\/}})\index{boolp} \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{nat-to-bv}}\,({\rm{carry}}\,({\it{c\/}})\index{carry} $+$ ({\it{i\/}} $+$ {\it{i\/}}), {\it{n\/}})\index{nat-to-bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\it{c\/}}, {\rm{nat-to-bv}}\,({\it{i\/}}, {\it{n\/}} $-\;1$)\index{nat-to-bv})\index{bitv}$\;${\bf  endif}\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  nat-to-bv-to-nat-wrong-size \\ \index{nat-to-bv-to-nat-wrong-size}
{\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}, {\it{n\/}})\index{nat-to-bv} $=$ {\rm{trunc}}\,({\it{a\/}}, {\it{n\/}})\index{trunc}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  nat-to-bv-ignores-remainder \\ \index{nat-to-bv-ignores-remainder}
{\rm{nat-to-bv}}\,({\it{i\/}} ${}${\bf{mod}}${}$ {\rm{exp}}\,({\tt{2}}, {\it{n\/}})\index{exp}, {\it{n\/}})\index{nat-to-bv} $=$ {\rm{nat-to-bv}}\,({\it{i\/}}, {\it{n\/}})\index{nat-to-bv}
\end{tabbing}


\noindent{\sc Event}:   Disable nat-to-bv-ignores-remainder.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  bv-adder-as-shifter \\ \index{bv-adder-as-shifter}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder}}\,({\it{c\/}}, {\it{a\/}}, {\it{a\/}})\index{bv-adder} \\ 
$=$$\;\;\;\;${\rm{nat-to-bv}}\,(\=\+{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}, \\ 
$1\;+$ {\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-adder-output-used-as-asl \\ \index{bv-adder-output-used-as-asl}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-output}}\,({\it{c\/}}, {\it{a\/}}, {\it{a\/}})\index{bv-adder-output} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf else }{\rm{bitv}}\,({\it{c\/}}, {\rm{trunc}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size} $-\;1$)\index{trunc})\index{bitv}$\;${\bf  endif}\-)\-\-
\end{tabbing}
             

\noindent{\sc Event}:   Disable bv-adder-output-used-as-asl.

\addvspace{18pt}
             
\begin{tabbing}{\sc Theorem}:  bitn-equiv-lessp \\ \index{bitn-equiv-lessp}
{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\rightarrow$ ({\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn} $=$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\not<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size} $-\;1$)\index{exp}))
\end{tabbing}
             
\begin{tabbing}{\sc Theorem}:  bv-adder-carry-out-used-as-asl \\ \index{bv-adder-carry-out-used-as-asl}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-carry-out}}\,({\it{c\/}}, {\it{a\/}}, {\it{a\/}})\index{bv-adder-carry-out} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{size}}\,({\it{a\/}})\index{size} $\simeq {\tt{0}}$$\;\;${\bf then }{\it{c\/}} \\ 
{\bf else }{\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn}$\;${\bf  endif}\-)\-\-
\end{tabbing}
             

\noindent{\sc Event}:   Disable bv-adder-carry-out-used-as-asl.

\addvspace{18pt}


\noindent{\sc Event}:   Disable bv-adder-as-shifter.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;           Boolean operation of ALU                                           ;; 
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\end{verbatim}\begin{tabbing}{\sc Theorem}:  bv-alu-cv-correct-boolean \\ \index{bv-alu-cv-correct-boolean}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{15}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} $=$ {\rm{bv-cv}}\,({\it{a\/}}, {\bf{f}}, {\bf{f}})\index{bv-cv}) \\ 
$\wedge$$\;\;\;\;$({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{14}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} $=$ {\rm{bv-cv}}\,({\rm{v-not}}\,({\it{a\/}})\index{v-not}, {\bf{f}}, {\bf{f}})\index{bv-cv}) \\ 
$\wedge$$\;\;\;\;$({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{13}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} $=$ {\rm{bv-cv}}\,({\rm{v-and}}\,({\it{a\/}}, {\it{b\/}})\index{v-and}, {\bf{f}}, {\bf{f}})\index{bv-cv}) \\ 
$\wedge$$\;\;\;\;$({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{12}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} $=$ {\rm{bv-cv}}\,({\rm{v-or}}\,({\it{a\/}}, {\it{b\/}})\index{v-or}, {\bf{f}}, {\bf{f}})\index{bv-cv}) \\ 
$\wedge$$\;\;\;\;$({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{11}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} $=$ {\rm{bv-cv}}\,({\rm{v-xor}}\,({\it{a\/}}, {\it{b\/}})\index{v-xor}, {\bf{f}}, {\bf{f}})\index{bv-cv}) \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{10}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} \\ 
$=$$\;\;\;\;${\rm{bv-cv}}\,({\rm{v-lsr}}\,({\it{a\/}})\index{v-lsr}, {\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}, {\bf{f}})\index{bv-cv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{9}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} \\ 
$=$$\;\;\;\;${\rm{bv-cv}}\,({\rm{v-asr}}\,({\it{a\/}})\index{v-asr}, {\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}, {\bf{f}})\index{bv-cv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{8}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} \\ 
$=$$\;\;\;\;${\rm{bv-cv}}\,(\=\+{\rm{v-ror}}\,({\it{a\/}}, {\it{c\/}})\index{v-ror}, \\ 
\=\+{\bf if }{\rm{size}}\,({\it{a\/}})\index{size} $\simeq {\tt{0}}$$\;\;${\bf then }{\it{c\/}} \\ 
{\bf else }{\rm{bitn}}\,({\it{a\/}}, {\tt{1}})\index{bitn}$\;${\bf  endif}\-, \\ 
{\bf{f}})\-\index{bv-cv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+({\it{a\/}} $=$ {\it{b\/}}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+({\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} $=$ {\rm{v-lsl}}\,({\it{a\/}})\index{v-lsl}) \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} \\ 
$=$$\;\;\;\;${\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn})\-)\-)\- \\ 
$\wedge$$\;\;\;\;$(\=\+({\it{a\/}} $=$ {\it{b\/}}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+({\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} $=$ {\rm{v-asl}}\,({\it{a\/}})\index{v-asl}) \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} \\ 
$=$$\;\;\;\;${\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn})\-)\-)\- \\ 
$\wedge$$\;\;\;\;$(\=\+({\it{a\/}} $=$ {\it{b\/}}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+({\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{2}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} $=$ {\rm{v-rol}}\,({\it{a\/}}, {\it{c\/}})\index{v-rol}) \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{2}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{size}}\,({\it{a\/}})\index{size} $\simeq {\tt{0}}$$\;\;${\bf then }{\it{c\/}} \\ 
{\bf else }{\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn}$\;${\bf  endif}\-)\-)\-)\-)\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;           Natural number ALU help lemmas                                     ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

                
\end{verbatim}\begin{tabbing}{\sc Theorem}:  v-append-quotient \\ \index{v-append-quotient}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\div$ {\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv} \\ 
$=$$\;\;\;\;${\rm{v-append}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{bitv}}\,({\bf{f}}, {\sc{btm}}\index{btm})\index{bitv})\index{v-append})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bit-interpretation-of-even-and-odd \\ \index{bit-interpretation-of-even-and-!odd}
(({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} ${}${\bf{mod}}${}$ {\tt{2}}) $=$ {\tt{0}}) $=$ ($\neg$ {\rm{bit}}\,({\it{a\/}})\index{bit})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  nat-to-bv-to-nat-hidden-to-accomodate-hands-off \\ \index{nat-to-bv-to-nat-hidden-to-acco!modate-hands-off}
({\it{x\/}} $-$ {\rm{bv-to-nat}}\,({\rm{nat-to-bv}}\,({\tt{0}}, {\it{n\/}})\index{nat-to-bv})\index{bv-to-nat}) $=$ {\rm{fix}}\,({\it{x\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  zero-not-less-than-anything \\ \index{zero-not-less-than-anything}
({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $-\;1$) $\not<$ {\rm{bv-to-nat}}\,({\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-to-nat}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  nat-interpretation-of-inc-bit-vector \\ \index{nat-interpretation-of-inc-bit-ve!ctor}
\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-output}}\,({\bf{t}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-adder-output} \\ 
$=$$\;\;\;\;$\=\+{\bf if }($1\;+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}) $<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} \\ 
{\bf then }{\rm{nat-to-bv}}\,($1\;+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}$\;${\bf  endif}\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable nat-interpretation-of-inc-bit-vector.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  nat-interpretation-of-inc-carry-out \\ \index{nat-interpretation-of-inc-carry!-out}
\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-carry-out}}\,({\bf{t}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-adder-carry-out} \\ 
$=$$\;\;\;\;$(($1\;+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}) $\not<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}))\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable nat-interpretation-of-inc-carry-out.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;           Natural number operation of ALU                                    ;; 
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  bv-alu-cv-correct-natural-number \\ \index{bv-alu-cv-correct-natural-numbe!r}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) $\wedge$ {\rm{boolp}}\,({\it{c\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+(\=\+{\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{10}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv} \\ 
$=$$\;\;\;\;${\rm{bv-cv}}\,(\=\+{\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\div$ {\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}, \\ 
({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} ${}${\bf{mod}}${}$ {\tt{2}}) $\not\simeq {\tt{0}}$, \\ 
{\bf{f}})\-\index{bv-cv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{7}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $\not<$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} \\ 
{\bf then }{\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $-$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,(\=\+\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} \\ 
$-$$\;\;\;\;$(\=\+{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} \\ 
$-$$\;\;\;\;${\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat})\-\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}$\;${\bf  endif}\-)\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{7}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} \\ 
$=$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $<$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{6}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $\not<$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
{\bf then }{\rm{nat-to-bv}}\,(\=\+\=\+{\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} \\ 
$-$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry})\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,(\=\+\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} \\ 
$-$$\;\;\;\;$(\=\+(\=\+{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} \\ 
$+$$\;\;\;\;${\rm{carry}}\,({\it{c\/}})\index{carry})\- \\ 
$-$$\;\;\;\;${\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat})\-\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}$\;${\bf  endif}\-)\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{6}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} \\ 
$=$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $<$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry})))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{5}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\simeq {\tt{0}}$ \\ 
{\bf then }{\rm{nat-to-bv}}\,({\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} $-\;1$, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $-\;1$, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}$\;${\bf  endif}\-)\- \\ 
$\wedge$$\;\;\;\;$({\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{5}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} $=$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\simeq {\tt{0}}$)) \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat}) \\ 
$<$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\- \\ 
{\bf then }{\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,(\=\+\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat}) \\ 
${}${\bf{mod}}${}$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}$\;${\bf  endif}\-)\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} \\ 
$=$$\;\;\;\;$(({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat}) $\not<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{2}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
$<$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\- \\ 
{\bf then }{\rm{nat-to-bv}}\,(\=\+\=\+{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} \\ 
$+$$\;\;\;\;${\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} \\ 
$+$$\;\;\;\;${\rm{carry}}\,({\it{c\/}})\index{carry}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,(\=\+\=\+(\=\+{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} \\ 
$+$$\;\;\;\;${\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} \\ 
$+$$\;\;\;\;${\rm{carry}}\,({\it{c\/}})\index{carry})\- \\ 
${}${\bf{mod}}${}$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{nat-to-bv}$\;${\bf  endif}\-)\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{2}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} \\ 
$=$$\;\;\;\;$(\=\+({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $+$ {\rm{bv-to-nat}}\,({\it{b\/}})\index{bv-to-nat} $+$ {\rm{carry}}\,({\it{c\/}})\index{carry}) \\ 
$\not<$$\;\;\;\;${\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\-)\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{1}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;$\=\+{\bf if }($1\;+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}) $<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} \\ 
{\bf then }{\rm{nat-to-bv}}\,($1\;+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}$\;${\bf  endif}\-)\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{1}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{c} \\ 
$=$$\;\;\;\;$(($1\;+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}) $\not<$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}))\-)\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;           Two's complement ALU help lemmas                                   ;; 
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  twos-complement-twos-complement \\ \index{twos-complement-twos-complement}
{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\rightarrow$ ({\rm{incr}}\,({\bf{t}}, {\rm{compl}}\,({\rm{incr}}\,({\bf{t}}, {\rm{compl}}\,({\it{a\/}})\index{compl})\index{incr})\index{compl})\index{incr} $=$ {\it{a\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-to-bv-to-tc-negative \\ \index{tc-to-bv-to-tc-negative}
({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\it{n\/}})) $\rightarrow$ ({\rm{tc-to-bv}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\it{n\/}})\index{tc-to-bv} $=$ {\it{a\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  v-asr-is-a-bitv \\ \index{v-asr-is-a-bitv}
{\rm{bitvp}}\,({\rm{v-asr}}\,({\it{a\/}})\index{v-asr})\index{bitvp}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-of-v-asr \\ \index{size-of-v-asr}
{\rm{size}}\,({\rm{v-asr}}\,({\it{a\/}})\index{v-asr})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-asr-divides-by-two-bridge \\ \index{bv-asr-divides-by-two-bridge}
{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\rightarrow$ ({\rm{tc-to-bv}}\,({\rm{mod2}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{mod2}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-to-bv} $=$ {\rm{bv-asr}}\,({\it{a\/}})\index{bv-asr})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-to-tc-to-bv-of-zero-is-zero \\ \index{bv-to-tc-to-bv-of-zero-is-zero}
{\rm{bv-to-tc}}\,({\rm{tc-to-bv}}\,({\tt{0}}, {\it{n\/}})\index{tc-to-bv})\index{bv-to-tc} $=$ {\tt{0}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-to-bv-is-not-btm-for-non-zero-size \\ \index{tc-to-bv-is-not-btm-for-non-zer!o-size}
({\it{n\/}} $\not\simeq {\tt{0}}$) $\rightarrow$ (({\rm{tc-to-bv}}\,({\tt{0}}, {\it{n\/}})\index{tc-to-bv} $=$ {\sc{btm}}\index{btm}) $=$ {\bf{f}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  nat-of-zero-is-tc-of-zero \\ \index{nat-of-zero-is-tc-of-zero}
{\rm{nat-to-bv}}\,({\tt{0}}, {\it{size\/}})\index{nat-to-bv} $=$ {\rm{tc-to-bv}}\,({\tt{0}}, {\it{size\/}})\index{tc-to-bv}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-fix-of-add \\ \index{tc-fix-of-add}
{\rm{tc-fix}}\,({\rm{add}}\,({\it{a\/}}, {\it{b\/}})\index{add})\index{tc-fix} $=$ {\rm{add}}\,({\rm{tc-fix}}\,({\it{a\/}})\index{tc-fix}, {\it{b\/}})\index{add}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-to-bv-of-bitv-not-btm \\ \index{tc-to-bv-of-bitv-not-btm}
(({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) $\wedge$ {\rm{bitvp}}\,({\it{a\/}})\index{bitvp}) $\rightarrow$ ({\rm{tc-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-to-bv} $\not=$ {\sc{btm}}\index{btm})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-inc-bit-vector \\ \index{tc-interpretation-of-inc-bit-ve!ctor}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-output}}\,({\bf{t}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-adder-output} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{1}})\index{add}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{1}})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{1}})\index{add}) \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\tt{1}}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\tt{1}}, $-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-interpretation-of-inc-bit-vector.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-dec-bit-vector \\ \index{tc-interpretation-of-dec-bit-ve!ctor}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-subtracter-output}}\,({\bf{t}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}, {\it{a\/}})\index{bv-subtracter-output} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{-1}})\index{add}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{-1}})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{-1}})\index{add}) \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\tt{-1}}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\tt{-1}}, $-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-interpretation-of-dec-bit-vector.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-inc-overflowp \\ \index{tc-interpretation-of-inc-overfl!owp}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-adder-overflowp}}\,({\bf{t}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-adder-overflowp} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{1}})\index{add}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep}))\-\-
\end{tabbing}
  

\noindent{\sc Event}:   Disable tc-interpretation-of-inc-overflowp.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-dec-overflowp \\ \index{tc-interpretation-of-dec-overfl!owp}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-subtracter-overflowp}}\,({\bf{t}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}, {\it{a\/}})\index{bv-subtracter-overflowp} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{-1}})\index{add}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep}))\-\-
\end{tabbing}
  

\noindent{\sc Event}:   Disable tc-interpretation-of-dec-overflowp.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-negation-output \\ \index{tc-interpretation-of-negation-o!utput}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-subtracter-output}}\,({\bf{f}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-subtracter-output} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,({\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep} \\ 
{\bf then }{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus}) \\ 
{\bf then }{\rm{add}}\,({\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, {\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-interpretation-of-negation-output.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  tc-interpretation-of-negation-overflowp \\ \index{tc-interpretation-of-negation-ove!rflowp}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{a\/}} $\not=$ {\sc{btm}}\index{btm})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{bv-subtracter-overflowp}}\,({\bf{f}}, {\it{a\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv})\index{bv-subtracter-overflowp} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,({\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep}))\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable tc-interpretation-of-negation-overflowp.

\addvspace{18pt}

\noindent{\sc Event}:   Disable nat-of-zero-is-tc-of-zero.

\addvspace{18pt}

\noindent{\sc Event}:   Disable tc-fix-of-add.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;           Two's complement operation of ALU                                  ;; 
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

                
\end{verbatim}\begin{tabbing}{\sc Theorem}:  alu-correct-twos-complement \\ \index{alu-correct-twos-complement}
\=\+(\=\+{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{a\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{b\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\it{b\/}} $\not=$ {\sc{btm}}\index{btm}) \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{9}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,({\rm{mod2}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{mod2}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-to-bv})\- \\ 
$\wedge$$\;\;\;\;$({\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{9}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{v} $=$ {\bf{f}}) \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{7}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\-\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\-\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\-\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{7}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{v} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep}))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{6}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{carry}}\,({\it{c\/}})\index{carry})\-\index{add})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\index{tc-minus})\-\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{carry}}\,({\it{c\/}})\index{carry})\-\index{add})\index{tc-minus})\-\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{carry}}\,({\it{c\/}})\index{carry})\-\index{add})\index{tc-minus})\-\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{carry}}\,({\it{c\/}})\index{carry})\-\index{add})\index{tc-minus})\-\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{6}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{v} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{tc-minus}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{carry}}\,({\it{c\/}})\index{carry})\-\index{add})\index{tc-minus})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep}))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{5}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{-1}})\index{add}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{-1}})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{-1}})\index{add}) \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\tt{-1}}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\tt{-1}}, $-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{5}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{v} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{-1}})\index{add}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep}))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{4}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}, \\ 
{\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{4}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{v} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,({\rm{tc-minus}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})\index{tc-minus}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep}))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc})\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc})\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\-\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{v} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc})\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep}))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{2}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\-\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{carry}}\,({\it{c\/}})\index{carry})\-\index{add})\-\index{add}) \\ 
{\bf then }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{carry}}\,({\it{c\/}})\index{carry}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add})\-\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,(\=\+{\rm{carry}}\,({\it{c\/}})\index{carry}, \\ 
$-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\-\index{add})\-\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{2}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{v} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,(\=\+{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{b\/}})\index{bv-to-tc}, {\rm{carry}}\,({\it{c\/}})\index{carry})\index{add})\-\index{add}, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-in-rangep}))\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{1}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{bv} \\ 
$=$$\;\;\;\;${\rm{tc-to-bv}}\,(\=\+\=\+{\bf if }{\rm{tc-in-rangep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{1}})\index{add}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep} \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{1}})\index{add} \\ 
{\bf elseif }{\rm{negativep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{1}})\index{add}) \\ 
{\bf then }{\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\rm{add}}\,({\tt{1}}, {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\index{add} \\ 
{\bf else }{\rm{add}}\,(\=\+{\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, \\ 
{\rm{add}}\,({\tt{1}}, $-$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp})\index{add})\-\index{add}$\;${\bf  endif}\-, \\ 
{\rm{size}}\,({\it{a\/}})\index{size})\-\index{tc-to-bv})\- \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\rm{nat-to-bv}}\,({\tt{1}}, {\tt{4}})\index{nat-to-bv})\index{bv-alu-cv})\index{v} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{tc-in-rangep}}\,({\rm{add}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc}, {\tt{1}})\index{add}, {\rm{size}}\,({\it{a\/}})\index{size})\index{tc-in-rangep}))\-)\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;          This file contains definitions and lemmas concerning the            ;;
;;          hardware necessary to build "big-machine".                          ;;
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;;          Miscellaneous lemmas                                                ;;
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\end{verbatim}\begin{tabbing}{\sc Theorem}:  size-bv-bv-alu-cv \\ \index{size-bv-bv-alu-cv}
{\rm{size}}\,({\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a\/}}, {\it{b\/}}, {\it{c\/}}, {\it{op-code\/}})\index{bv-alu-cv})\index{bv})\index{size} $=$ {\rm{size}}\,({\it{a\/}})\index{size}
\end{tabbing}


\noindent{\sc Event}:   Disable bv-alu-cv.

\addvspace{18pt}


\noindent{\sc Event}:   Disable bv-alu-cv-with-ifs.

\addvspace{18pt}

\begin{tabbing}{\sc Definition}:\index{fix-bool} \\  
\=\+{\rm{fix-bool}}\,({\it{x\/}})\index{fix-bool} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\bf{f}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{properp} \\  
\=\+{\rm{properp}}\,({\it{x\/}})\index{properp} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\it{x\/}} $=$ {\bf{nil}} \\ 
{\bf else }{\rm{properp}}\,({\rm{cdr}}\,({\it{x\/}}))\index{properp}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{append} \\  
\=\+{\rm{append}}\,({\it{x\/}}, {\it{y\/}}) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{x\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\it{y\/}} \\ 
{\bf else }{\rm{cons}}\,({\rm{car}}\,({\it{x\/}}), {\rm{append}}\,({\rm{cdr}}\,({\it{x\/}}), {\it{y\/}}))$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  assoc-of-append \\ \index{assoc-of-append}
{\rm{append}}\,({\rm{append}}\,({\it{a\/}}, {\it{b\/}}), {\it{c\/}}) $=$ {\rm{append}}\,({\it{a\/}}, {\rm{append}}\,({\it{b\/}}, {\it{c\/}}))
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  length-0 \\ \index{length-0}
({\rm{length}}\,({\it{x\/}})\index{length} $=$ {\tt{0}}) $=$ ({\it{x\/}} $\simeq\;${{\bf{nil}}}${}$)
\end{tabbing}


\begin{tabbing}{\sc Definition}:\index{v-nat-dec} \\  
\=\+{\rm{v-nat-dec}}\,({\it{a\/}})\index{v-nat-dec} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\simeq {\tt{0}}$$\;\;${\bf then }{\rm{nat-to-bv}}\,({\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp} $-\;1$, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv} \\ 
{\bf else }{\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $-\;1$, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}$\;${\bf  endif}\-\-
\end{tabbing}                    \begin{verbatim}; around is received.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{v-nat-inc}$\;\;$
{\rm{v-nat-inc}}\,({\it{a\/}})\index{v-nat-inc} $=$ {\rm{nat-to-bv}}\,($1\;+$ {\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat}, {\rm{size}}\,({\it{a\/}})\index{size})\index{nat-to-bv}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-nat-dec \\ \index{size-v-nat-dec}
{\rm{size}}\,({\rm{v-nat-dec}}\,({\it{x\/}})\index{v-nat-dec})\index{size} $=$ {\rm{size}}\,({\it{x\/}})\index{size}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-nat-inc \\ \index{size-v-nat-inc}
{\rm{size}}\,({\rm{v-nat-inc}}\,({\it{x\/}})\index{v-nat-inc})\index{size} $=$ {\rm{size}}\,({\it{x\/}})\index{size}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;          Memory accessors                                                    ;;
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\end{verbatim}\begin{tabbing}{\sc Definition}:\index{nth} \\  
\=\+{\rm{nth}}\,({\it{n\/}}, {\it{lst\/}})\index{nth} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\rm{car}}\,({\it{lst\/}}) \\ 
{\bf else }{\rm{nth}}\,({\it{n\/}} $-\;1$, {\rm{cdr}}\,({\it{lst\/}}))\index{nth}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-nth}$\;\;$
{\rm{v-nth}}\,({\it{v-n\/}}, {\it{lst\/}})\index{v-nth} $=$ {\rm{nth}}\,({\rm{bv-to-nat}}\,({\it{v-n\/}})\index{bv-to-nat}, {\it{lst\/}})\index{nth}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{update-v} \\  
\=\+{\rm{update-v}}\,({\it{c\/}}, {\it{cell\/}}, {\it{value\/}})\index{update-v} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{truep}}\,({\it{c\/}})$\;\;${\bf then }{\it{value\/}} \\ 
{\bf else }{\it{cell\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{update-nth} \\  
\=\+{\rm{update-nth}}\,({\it{c\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{value\/}})\index{update-nth} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{truep}}\,({\it{c\/}}) $\wedge$ {\rm{listp}}\,({\it{lst\/}}) \\ 
{\bf then }\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\rm{cons}}\,({\it{value\/}}, {\rm{cdr}}\,({\it{lst\/}})) \\ 
{\bf else }{\rm{cons}}\,({\rm{car}}\,({\it{lst\/}}), {\rm{update-nth}}\,({\it{c\/}}, {\it{n\/}} $-\;1$, {\rm{cdr}}\,({\it{lst\/}}), {\it{value\/}})\index{update-nth})$\;${\bf  endif}\- \\ 
{\bf else }{\it{lst\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{update-v-nth} \\  
{\rm{update-v-nth}}\,({\it{c\/}}, {\it{v-n\/}}, {\it{lst\/}}, {\it{value\/}})\index{update-v-nth} $=$ {\rm{update-nth}}\,({\it{c\/}}, {\rm{bv-to-nat}}\,({\it{v-n\/}})\index{bv-to-nat}, {\it{lst\/}}, {\it{value\/}})\index{update-nth}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  length-update-nth \\ \index{length-update-nth}
{\rm{length}}\,({\rm{update-nth}}\,({\it{c\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{value\/}})\index{update-nth})\index{length} $=$ {\rm{length}}\,({\it{lst\/}})\index{length}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  length-update-v-nth \\ \index{length-update-v-nth}
{\rm{length}}\,({\rm{update-v-nth}}\,({\it{c\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{value\/}})\index{update-v-nth})\index{length} $=$ {\rm{length}}\,({\it{lst\/}})\index{length}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  listp-update-nth \\ \index{listp-update-nth}
{\rm{listp}}\,({\rm{update-nth}}\,({\it{c\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{value\/}})\index{update-nth}) $=$ {\rm{listp}}\,({\it{lst\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  listp-update-v-nth \\ \index{listp-update-v-nth}
{\rm{listp}}\,({\rm{update-v-nth}}\,({\it{c\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{value\/}})\index{update-v-nth}) $=$ {\rm{listp}}\,({\it{lst\/}})
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Zero and Negative flag interpretation lemmas                        ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-bv-nzerop} \\  
\=\+{\rm{b-bv-nzerop}}\,({\it{a\/}})\index{b-bv-nzerop} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\rm{b-or}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{b-bv-nzerop}}\,({\rm{vec}}\,({\it{a\/}})\index{vec})\index{b-bv-nzerop})\index{b-or}$\;${\bf  endif}\- \\ 
{\bf else }{\bf{f}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-bv-zerop}$\;\;$
{\rm{b-bv-zerop}}\,({\it{a\/}})\index{b-bv-zerop} $=$ {\rm{b-not}}\,({\rm{b-bv-nzerop}}\,({\it{a\/}})\index{b-bv-nzerop})\index{b-not}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-zerop} \\  
\=\+{\rm{v-zerop}}\,({\it{a\/}})\index{v-zerop} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }({\rm{bit}}\,({\it{a\/}})\index{bit} $=$ {\bf{f}}) $\wedge$ {\rm{v-zerop}}\,({\rm{vec}}\,({\it{a\/}})\index{vec})\index{v-zerop}$\;${\bf  endif}\- \\ 
{\bf else }{\bf{t}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  b-bv-zerop-equal-v-zerop \\ \index{b-bv-zerop-equal-v-zerop}
{\rm{b-bv-zerop}}\,({\it{a\/}})\index{b-bv-zerop} $=$ {\rm{v-zerop}}\,({\it{a\/}})\index{v-zerop}
\end{tabbing}


\begin{verbatim};  The following are the natural number and tc intepretation lemmas for
;  the zero flag.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  v-zerop-equal-bv-to-nat-zero \\ \index{v-zerop-equal-bv-to-nat-zero}
{\rm{v-zerop}}\,({\it{a\/}})\index{v-zerop} $=$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $\simeq {\tt{0}}$)
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  v-zerop-equal-bv-to-tc-zero \\ \index{v-zerop-equal-bv-to-tc-zero}
{\rm{v-zerop}}\,({\it{a\/}})\index{v-zerop} $=$ ({\tt{0}} $=$ {\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})
\end{tabbing}


\noindent{\sc Event}:   Disable v-zerop-equal-bv-to-nat-zero.

\addvspace{18pt}

\noindent{\sc Event}:   Disable v-zerop-equal-bv-to-tc-zero.

\addvspace{18pt}

\begin{verbatim};  The following is the tc interpretation lemma for the negative flag.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  n-flag-equals-negativep \\ \index{n-flag-equals-negativep}
{\rm{bitn}}\,({\it{a\/}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{bitn} $=$ {\rm{negativep}}\,({\rm{bv-to-tc}}\,({\it{a\/}})\index{bv-to-tc})
\end{tabbing}


\noindent{\sc Event}:   Disable n-flag-equals-negativep.

\addvspace{18pt}



\begin{tabbing}{\sc Definition}:\index{bv-equal} \\  
\=\+{\rm{bv-equal}}\,({\it{a\/}}, {\it{b\/}})\index{bv-equal} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp} \\ 
{\bf then }\=\+{\bf if }{\it{a\/}} $=$ {\sc{btm}}\index{btm}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\rm{b-and}}\,({\rm{b-equv}}\,({\rm{bit}}\,({\it{a\/}})\index{bit}, {\rm{bit}}\,({\it{b\/}})\index{bit})\index{b-equv}, {\rm{bv-equal}}\,({\rm{vec}}\,({\it{a\/}})\index{vec}, {\rm{vec}}\,({\it{b\/}})\index{vec})\index{bv-equal})\index{b-and}$\;${\bf  endif}\- \\ 
{\bf else }{\bf{f}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-equal-is-equal \\ \index{bv-equal-is-equal}
\=\+({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ {\rm{bitvp}}\,({\it{b\/}})\index{bitvp} $\wedge$ ({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\rm{size}}\,({\it{b\/}})\index{size})) \\ 
$\rightarrow$$\;\;\;\;$({\rm{bv-equal}}\,({\it{a\/}}, {\it{b\/}})\index{bv-equal} $=$ ({\it{a\/}} $=$ {\it{b\/}}))\-
\end{tabbing}


\noindent{\sc Event}:   Disable bv-equal-is-equal.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Assumptions made about the various registers                        ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{nxsz}$\;\;$
{\sc{nxsz}}\index{nxsz} $=$ {\tt{4}}
\end{tabbing}                               \begin{verbatim}; width of micro address reg

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{machine-size}$\;\;$
{\sc{machine-size}}\index{machine-size} $=$ {\tt{16}}
\end{tabbing}                      \begin{verbatim}; Word width of micro-processor
\end{verbatim}
\newpage
\begin{verbatim}

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Register, RAMP, and ROMP recognizer                                 ;;
;;                                                                              ;;
;;          A ram and rom checker are presented below and is used to ensure     ;;
;;          that RAM and ROM (constant function) have certain properties.       ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{sizep}$\;\;$
{\rm{sizep}}\,({\it{register\/}}, {\it{width\/}})\index{sizep} $=$ ({\rm{size}}\,({\it{register\/}})\index{size} $=$ {\it{width\/}})
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{every-member-sizep} \\  
\=\+{\rm{every-member-sizep}}\,({\it{lst\/}}, {\it{n\/}})\index{every-member-sizep} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{lst\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\rm{sizep}}\,({\rm{car}}\,({\it{lst\/}}), {\it{n\/}})\index{sizep} $\wedge$ {\rm{every-member-sizep}}\,({\rm{cdr}}\,({\it{lst\/}}), {\it{n\/}})\index{every-member-sizep}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{ramp} \\  
\=\+{\rm{ramp}}\,({\it{ram\/}}, {\it{width\/}}, {\it{locations\/}})\index{ramp} \\ 
$=$$\;\;\;\;$(({\rm{length}}\,({\it{ram\/}})\index{length} $=$ {\it{locations\/}}) $\wedge$ {\rm{every-member-sizep}}\,({\it{ram\/}}, {\it{width\/}})\index{every-member-sizep})\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{romp} \\  
\=\+{\rm{romp}}\,({\it{rom\/}}, {\it{width\/}}, {\it{locations\/}})\index{romp} \\ 
$=$$\;\;\;\;$(({\rm{length}}\,({\it{rom\/}})\index{length} $=$ {\it{locations\/}}) $\wedge$ {\rm{every-member-sizep}}\,({\it{rom\/}}, {\it{width\/}})\index{every-member-sizep})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  every-member-sizep-implies-size-nth \\ \index{every-member-sizep-implies-size!-nth}
\=\+(({\it{n\/}} $<$ {\rm{length}}\,({\it{lst\/}})\index{length}) $\wedge$ {\rm{every-member-sizep}}\,({\it{lst\/}}, {\it{width\/}})\index{every-member-sizep}) \\ 
$\rightarrow$$\;\;\;\;$({\rm{size}}\,({\rm{nth}}\,({\it{n\/}}, {\it{lst\/}})\index{nth})\index{size} $=$ {\it{width\/}})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  every-member-sizep-implies-size-nth-machine-size \\ \index{every-member-sizep-implies-size!-nth-machine-size}
\=\+(({\it{n\/}} $<$ {\rm{length}}\,({\it{lst\/}})\index{length}) $\wedge$ {\rm{every-member-sizep}}\,({\it{lst\/}}, {\sc{machine-size}}\index{machine-size})\index{every-member-sizep}) \\ 
$\rightarrow$$\;\;\;\;$({\rm{size}}\,({\rm{nth}}\,({\it{n\/}}, {\it{lst\/}})\index{nth})\index{size} $=$ {\sc{machine-size}}\index{machine-size})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  every-member-sizep-implies-size-nth-0 \\ \index{every-member-sizep-implies-size!-nth-0}
\=\+({\rm{every-member-sizep}}\,({\it{lst\/}}, {\it{width\/}})\index{every-member-sizep} $\wedge$ ({\tt{0}} $<$ {\rm{length}}\,({\it{lst\/}})\index{length})) \\ 
$\rightarrow$$\;\;\;\;$({\rm{size}}\,({\rm{car}}\,({\it{lst\/}}))\index{size} $=$ {\it{width\/}})\-
\end{tabbing}


\noindent{\sc Event}:   Disable boolp.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Op-code accessors                                                   ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{bv-op-code} \\  
\=\+{\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code} \\ 
$=$$\;\;\;\;${\rm{bitv}}\,(\=\+{\rm{bitn}}\,({\it{i-reg\/}}, {\tt{13}})\index{bitn}, \\ 
{\rm{bitv}}\,(\=\+{\rm{bitn}}\,({\it{i-reg\/}}, {\tt{14}})\index{bitn}, \\ 
{\rm{bitv}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{15}})\index{bitn}, {\rm{bitv}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{16}})\index{bitn}, {\sc{btm}}\index{btm})\index{bitv})\index{bitv})\-\index{bitv})\-\index{bitv}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-move-op}$\;\;$
{\rm{b-move-op}}\,({\it{i-reg\/}})\index{b-move-op} $=$ {\rm{bitn}}\,({\it{i-reg\/}}, {\tt{12}})\index{bitn}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-cc-set}$\;\;$
{\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set} $=$ {\rm{bitn}}\,({\it{i-reg\/}}, {\tt{11}})\index{bitn}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-direct-reg-b} \\  
{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b} $=$ {\rm{b-nor}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{9}})\index{bitn}, {\rm{bitn}}\,({\it{i-reg\/}}, {\tt{10}})\index{bitn})\index{b-nor}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-indirect-reg-b} \\  
{\rm{b-indirect-reg-b}}\,({\it{i-reg\/}})\index{b-indirect-reg-b} $=$ {\rm{b-and}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{9}})\index{bitn}, {\rm{b-not}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{10}})\index{bitn})\index{b-not})\index{b-and}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-indirect-reg-b-dec} \\  
{\rm{b-indirect-reg-b-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-dec} $=$ {\rm{b-and}}\,({\rm{b-not}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{9}})\index{bitn})\index{b-not}, {\rm{bitn}}\,({\it{i-reg\/}}, {\tt{10}})\index{bitn})\index{b-and}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-indirect-reg-b-inc} \\  
{\rm{b-indirect-reg-b-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-inc} $=$ {\rm{b-and}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{9}})\index{bitn}, {\rm{bitn}}\,({\it{i-reg\/}}, {\tt{10}})\index{bitn})\index{b-and}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-oprd-b} \\  
\=\+{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b} \\ 
$=$$\;\;\;\;${\rm{bitv}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{6}})\index{bitn}, {\rm{bitv}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{7}})\index{bitn}, {\rm{bitv}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{8}})\index{bitn}, {\sc{btm}}\index{btm})\index{bitv})\index{bitv})\index{bitv}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-direct-reg-a} \\  
{\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a} $=$ {\rm{b-nor}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{4}})\index{bitn}, {\rm{bitn}}\,({\it{i-reg\/}}, {\tt{5}})\index{bitn})\index{b-nor}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-indirect-reg-a} \\  
{\rm{b-indirect-reg-a}}\,({\it{i-reg\/}})\index{b-indirect-reg-a} $=$ {\rm{b-and}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{4}})\index{bitn}, {\rm{b-not}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{5}})\index{bitn})\index{b-not})\index{b-and}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-indirect-reg-a-dec} \\  
{\rm{b-indirect-reg-a-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-dec} $=$ {\rm{b-and}}\,({\rm{b-not}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{4}})\index{bitn})\index{b-not}, {\rm{bitn}}\,({\it{i-reg\/}}, {\tt{5}})\index{bitn})\index{b-and}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-indirect-reg-a-inc} \\  
{\rm{b-indirect-reg-a-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-inc} $=$ {\rm{b-and}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{4}})\index{bitn}, {\rm{bitn}}\,({\it{i-reg\/}}, {\tt{5}})\index{bitn})\index{b-and}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-oprd-a} \\  
\=\+{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a} \\ 
$=$$\;\;\;\;${\rm{bitv}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{1}})\index{bitn}, {\rm{bitv}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{2}})\index{bitn}, {\rm{bitv}}\,({\rm{bitn}}\,({\it{i-reg\/}}, {\tt{3}})\index{bitn}, {\sc{btm}}\index{btm})\index{bitv})\index{bitv})\index{bitv}\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Sub-functions for FM8501                                            ;;
;;                                                                              ;;
;;          NOTE:  Many definitions below are presented in pairs.  A hardware   ;;
;;                 version is presented along with a version that is more       ;;
;;                 agreeable to the theorem-prover.  The second of these        ;;
;;                 paired definitions is has a "WITH-IFS" ending.  Not all      ;;
;;                 of the hardware functions have a "WITH-IFS" pair.            ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{bv-alu-op-code} \\  
\=\+{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code} \\ 
$=$$\;\;\;\;${\rm{bv-if}}\,({\rm{b-move-op}}\,({\it{i-reg\/}})\index{b-move-op}, {\rm{nat-to-bv}}\,({\tt{0}}, {\tt{4}})\index{nat-to-bv}, {\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code})\index{bv-if}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-store-alu-result} \\  
\=\+{\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result} \\ 
$=$$\;\;\;\;${\rm{b-or}}\,(\=\+{\rm{b-or}}\,({\rm{b-not}}\,({\rm{b-move-op}}\,({\it{i-reg\/}})\index{b-move-op})\index{b-not}, {\rm{bitn}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\tt{4}})\index{bitn})\index{b-or}, \\ 
{\rm{b-or}}\,(\=\+{\rm{b-or}}\,(\=\+{\rm{b-or}}\,(\=\+{\rm{b-and}}\,(\=\+{\rm{b-not}}\,({\it{c-flag\/}})\index{b-not}, \\ 
{\rm{bv-equal}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\rm{nat-to-bv}}\,({\tt{0}}, {\tt{4}})\index{nat-to-bv})\index{bv-equal})\-\index{b-and}, \\ 
{\rm{b-and}}\,(\=\+{\it{c-flag\/}}, \\ 
{\rm{bv-equal}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\rm{nat-to-bv}}\,({\tt{1}}, {\tt{4}})\index{nat-to-bv})\index{bv-equal})\-\index{b-and})\-\index{b-or}, \\ 
{\rm{b-or}}\,(\=\+{\rm{b-and}}\,(\=\+{\rm{b-not}}\,({\it{v-flag\/}})\index{b-not}, \\ 
{\rm{bv-equal}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\rm{nat-to-bv}}\,({\tt{2}}, {\tt{4}})\index{nat-to-bv})\index{bv-equal})\-\index{b-and}, \\ 
{\rm{b-and}}\,(\=\+{\it{v-flag\/}}, \\ 
{\rm{bv-equal}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\rm{nat-to-bv}}\,({\tt{3}}, {\tt{4}})\index{nat-to-bv})\index{bv-equal})\-\index{b-and})\-\index{b-or})\-\index{b-or}, \\ 
{\rm{b-or}}\,(\=\+{\rm{b-or}}\,(\=\+{\rm{b-and}}\,(\=\+{\rm{b-not}}\,({\it{z-flag\/}})\index{b-not}, \\ 
{\rm{bv-equal}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\rm{nat-to-bv}}\,({\tt{4}}, {\tt{4}})\index{nat-to-bv})\index{bv-equal})\-\index{b-and}, \\ 
{\rm{b-and}}\,(\=\+{\it{z-flag\/}}, \\ 
{\rm{bv-equal}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\rm{nat-to-bv}}\,({\tt{5}}, {\tt{4}})\index{nat-to-bv})\index{bv-equal})\-\index{b-and})\-\index{b-or}, \\ 
{\rm{b-or}}\,(\=\+{\rm{b-and}}\,(\=\+{\rm{b-not}}\,({\it{n-flag\/}})\index{b-not}, \\ 
{\rm{bv-equal}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\rm{nat-to-bv}}\,({\tt{6}}, {\tt{4}})\index{nat-to-bv})\index{bv-equal})\-\index{b-and}, \\ 
{\rm{b-and}}\,(\=\+{\it{n-flag\/}}, \\ 
{\rm{bv-equal}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\rm{nat-to-bv}}\,({\tt{7}}, {\tt{4}})\index{nat-to-bv})\index{bv-equal})\-\index{b-and})\-\index{b-or})\-\index{b-or})\-\index{b-or})\-\index{b-or}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-store-alu-result-with-ifs} \\  
\=\+{\rm{b-store-alu-result-with-ifs}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result-with-ifs} \\ 
$=$$\;\;\;\;$(\=\+($\neg$ {\rm{b-move-op}}\,({\it{i-reg\/}})\index{b-move-op}) \\ 
$\vee$$\;\;\;\;${\rm{bitn}}\,({\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code}, {\tt{4}})\index{bitn} \\ 
$\vee$$\;\;\;\;$(\=\+{\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code} \\ 
$=$$\;\;\;\;${\rm{nat-to-bv}}\,(\=\+\=\+{\bf if }{\it{c-flag\/}}$\;\;${\bf then }{\tt{1}} \\ 
{\bf else }{\tt{0}}$\;${\bf  endif}\-, \\ 
{\tt{4}})\-\index{nat-to-bv})\- \\ 
$\vee$$\;\;\;\;$(\=\+{\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code} \\ 
$=$$\;\;\;\;${\rm{nat-to-bv}}\,(\=\+\=\+{\bf if }{\it{v-flag\/}}$\;\;${\bf then }{\tt{3}} \\ 
{\bf else }{\tt{2}}$\;${\bf  endif}\-, \\ 
{\tt{4}})\-\index{nat-to-bv})\- \\ 
$\vee$$\;\;\;\;$(\=\+{\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code} \\ 
$=$$\;\;\;\;${\rm{nat-to-bv}}\,(\=\+\=\+{\bf if }{\it{z-flag\/}}$\;\;${\bf then }{\tt{5}} \\ 
{\bf else }{\tt{4}}$\;${\bf  endif}\-, \\ 
{\tt{4}})\-\index{nat-to-bv})\- \\ 
$\vee$$\;\;\;\;$(\=\+{\rm{bv-op-code}}\,({\it{i-reg\/}})\index{bv-op-code} \\ 
$=$$\;\;\;\;${\rm{nat-to-bv}}\,(\=\+\=\+{\bf if }{\it{n-flag\/}}$\;\;${\bf then }{\tt{7}} \\ 
{\bf else }{\tt{6}}$\;${\bf  endif}\-, \\ 
{\tt{4}})\-\index{nat-to-bv})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  b-store-alu-result-ifs \\ \index{b-store-alu-result-ifs}
\=\+{\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result} \\ 
$=$$\;\;\;\;${\rm{b-store-alu-result-with-ifs}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result-with-ifs}\-
\end{tabbing}


\noindent{\sc Event}:   Disable b-store-alu-result.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Micro-rom                                                           ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{make-micro-word} \\  
\=\+{\rm{make-micro-word}}\,({\it{l\/}})\index{make-micro-word} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{l\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\sc{btm}}\index{btm} \\ 
{\bf elseif }{\rm{cdr}}\,({\it{l\/}}) $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\rm{nat-to-bv}}\,({\rm{car}}\,({\it{l\/}}), {\sc{nxsz}}\index{nxsz})\index{nat-to-bv} \\ 
{\bf else }{\rm{bitv}}\,(\=\+\=\+{\bf if }{\rm{car}}\,({\it{l\/}}) $=$ {\tt{'}}{\tt{t}}$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\bf{f}}$\;${\bf  endif}\-, \\ 
{\rm{make-micro-word}}\,({\rm{cdr}}\,({\it{l\/}}))\index{make-micro-word})\-\index{bitv}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{make-micro-rom} \\  
\=\+{\rm{make-micro-rom}}\,({\it{l\/}})\index{make-micro-rom} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{l\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\bf{nil}} \\ 
{\bf else }{\rm{cons}}\,({\rm{make-micro-word}}\,({\rm{car}}\,({\it{l\/}}))\index{make-micro-word}, {\rm{make-micro-rom}}\,({\rm{cdr}}\,({\it{l\/}}))\index{make-micro-rom})$\;${\bf  endif}\-\-
\end{tabbing}


\begin{tabbing}{\sc Definition}:\index{micro-store} \\  
\=\+{\sc{micro-store}}\index{micro-store} \\ 
$=$$\;\;\;\;${\rm{make-micro-rom}}\,({\tt{'}}{\tt{(}}\=\+{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{1}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{2}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{3}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{4}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{5}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{6}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{7}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{8}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{9}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{10}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{11}}{\tt{)}} \\ 
{\tt{(}}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{12}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{13}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{1}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{0}}{\tt{)}} \\ 
{\tt{(}}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{t}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{f}}{\tt{ }}{\tt{0}}{\tt{)}}{\tt{)}}\-)\index{make-micro-rom}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{micro-rom}$\;\;$
{\rm{micro-rom}}\,({\it{addr\/}})\index{micro-rom} $=$ {\rm{v-nth}}\,({\it{addr\/}}, {\sc{micro-store}}\index{micro-store})\index{v-nth}
\end{tabbing}


\begin{verbatim};  Accessors for data in the ROM named "micro-store".

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-dout-incdec}$\;\;$
{\rm{b-dout-incdec}}\,({\it{x\/}})\index{b-dout-incdec} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{1}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Data out reg or address unit
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-force-inc}$\;\;$
{\rm{b-force-inc}}\,({\it{x\/}})\index{b-force-inc} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{2}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Force increment for address
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-en-no-store}$\;\;$
{\rm{b-en-no-store}}\,({\it{x\/}})\index{b-en-no-store} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{3}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Let "NO-STORE" effect sequencer
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-ir-mem-ref}$\;\;$
{\rm{b-ir-mem-ref}}\,({\it{x\/}})\index{b-ir-mem-ref} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{4}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Memory reference for instruction
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-oprda-oprdb}$\;\;$
{\rm{b-oprda-oprdb}}\,({\it{x\/}})\index{b-oprda-oprdb} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{5}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Select operand A or operand B
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-pc-regnum}$\;\;$
{\rm{b-pc-regnum}}\,({\it{x\/}})\index{b-pc-regnum} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{6}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Select PC or register in file
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-postinc}$\;\;$
{\rm{b-postinc}}\,({\it{x\/}})\index{b-postinc} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{7}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Post-increment address mode
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-predec}$\;\;$
{\rm{b-predec}}\,({\it{x\/}})\index{b-predec} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{8}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Pre-decrement address mode
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-rd}$\;\;$
{\rm{b-rd}}\,({\it{x\/}})\index{b-rd} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{9}})\index{bitn}
\end{tabbing}  \begin{verbatim}; Read cycle
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-seq}$\;\;$
{\rm{b-seq}}\,({\it{x\/}})\index{b-seq} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{10}})\index{bitn}
\end{tabbing} \begin{verbatim}; Sequence micro-address register
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-we-a-reg}$\;\;$
{\rm{b-we-a-reg}}\,({\it{x\/}})\index{b-we-a-reg} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{11}})\index{bitn}
\end{tabbing} \begin{verbatim}; Write enable A register
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-we-addr-out}$\;\;$
{\rm{b-we-addr-out}}\,({\it{x\/}})\index{b-we-addr-out} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{12}})\index{bitn}
\end{tabbing} \begin{verbatim}; Write enable address-out register
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-we-b-reg}$\;\;$
{\rm{b-we-b-reg}}\,({\it{x\/}})\index{b-we-b-reg} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{13}})\index{bitn}
\end{tabbing} \begin{verbatim}; Write enable B register
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-we-alu-result}$\;\;$
{\rm{b-we-alu-result}}\,({\it{x\/}})\index{b-we-alu-result} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{14}})\index{bitn}
\end{tabbing} \begin{verbatim}; WE DATA-OUT, CC-REG, NO-STORE
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-we-ir}$\;\;$
{\rm{b-we-ir}}\,({\it{x\/}})\index{b-we-ir} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{15}})\index{bitn}
\end{tabbing} \begin{verbatim}; Write enable instruction register
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-wr}$\;\;$
{\rm{b-wr}}\,({\it{x\/}})\index{b-wr} $=$ {\rm{bitn}}\,({\it{x\/}}, {\tt{16}})\index{bitn}
\end{tabbing} \begin{verbatim}; Write cycle
\end{verbatim}\begin{tabbing}{\sc Definition}:\index{bv-next} \\  
\=\+{\rm{bv-next}}\,({\it{x\/}})\index{bv-next} \\ 
$=$$\;\;\;\;${\rm{bitv}}\,(\=\+{\rm{bitn}}\,({\it{x\/}}, {\tt{17}})\index{bitn}, \\ 
{\rm{bitv}}\,({\rm{bitn}}\,({\it{x\/}}, {\tt{18}})\index{bitn}, {\rm{bitv}}\,({\rm{bitn}}\,({\it{x\/}}, {\tt{19}})\index{bitn}, {\rm{bitv}}\,({\rm{bitn}}\,({\it{x\/}}, {\tt{20}})\index{bitn}, {\sc{btm}}\index{btm})\index{bitv})\index{bitv})\index{bitv})\-\index{bitv}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{right-bv-next-size} \\  
\=\+{\rm{right-bv-next-size}}\,({\it{lst\/}})\index{right-bv-next-size} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{lst\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }\=\+({\rm{size}}\,({\rm{bv-next}}\,({\rm{car}}\,({\it{lst\/}}))\index{bv-next})\index{size} $=$ {\sc{nxsz}}\index{nxsz}) \\ 
$\wedge$$\;\;\;\;${\rm{right-bv-next-size}}\,({\rm{cdr}}\,({\it{lst\/}}))\index{right-bv-next-size}\-$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-bv-next-micro-rom-lemma \\ \index{size-bv-next-micro-rom-lemma}
{\rm{size}}\,({\rm{bv-next}}\,({\it{x\/}})\index{bv-next})\index{size} $=$ {\tt{4}}
\end{tabbing}


\noindent{\sc Event}:   Disable micro-rom.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Hardware variable and constant assumptions for FM8501.              ;;
;;                                                                              ;;
;;      The following definition describes the assumptions about the various    ;;
;;      registers (variables) and the ROM used in the construction of the       ;;
;;      FM8501 microprocessor.                                                  ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{standard-hyps} \\  
\=\+{\rm{standard-hyps}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}})\-\index{standard-hyps} \\ 
$=$$\;\;\;\;$(\=\+{\rm{romp}}\,({\sc{micro-store}}\index{micro-store}, {\tt{20}}, {\rm{exp}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{exp})\index{romp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{mar\/}}, {\sc{nxsz}}\index{nxsz})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{read\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{write\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{dtack\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{reset\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{no-store\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{a-reg\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{b-reg\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{i-reg\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{visual-mem\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\tt{16}})\index{exp})\index{ramp})\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Miscellanous lemmas                                                 ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  every-member-sizep-implies-bitvp \\ \index{every-member-sizep-implies-bitvp}
\=\+({\rm{every-member-sizep}}\,({\it{lst\/}}, {\it{width\/}})\index{every-member-sizep} $\wedge$ ({\it{n\/}} $<$ {\rm{length}}\,({\it{lst\/}})\index{length}) $\wedge$ ({\it{width\/}} $\not\simeq {\tt{0}}$)) \\ 
$\rightarrow$$\;\;\;\;${\rm{bitvp}}\,({\rm{nth}}\,({\it{n\/}}, {\it{lst\/}})\index{nth})\index{bitvp}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  every-member-sizep-implies-bitvp-machine-size \\ \index{every-member-sizep-implies-bitvp!-machine-size}
\=\+({\rm{every-member-sizep}}\,({\it{lst\/}}, {\sc{machine-size}}\index{machine-size})\index{every-member-sizep} $\wedge$ ({\it{n\/}} $<$ {\rm{length}}\,({\it{lst\/}})\index{length})) \\ 
$\rightarrow$$\;\;\;\;${\rm{bitvp}}\,({\rm{nth}}\,({\it{n\/}}, {\it{lst\/}})\index{nth})\index{bitvp}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  sizep-implies-bitvp \\ \index{sizep-implies-bitvp}
({\rm{size}}\,({\it{a\/}})\index{size} $=$ ($1\;+$ {\it{n\/}})) $\rightarrow$ {\rm{bitvp}}\,({\it{a\/}})\index{bitvp}
\end{tabbing}


\begin{verbatim};  The following lemma subsumes trunc-size.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  trunc-size-bridge \\ \index{trunc-size-bridge}
({\rm{bitvp}}\,({\it{a\/}})\index{bitvp} $\wedge$ ({\it{n\/}} $=$ {\rm{size}}\,({\it{a\/}})\index{size})) $\rightarrow$ ({\rm{trunc}}\,({\it{a\/}}, {\it{n\/}})\index{trunc} $=$ {\it{a\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  b-if-works \\ \index{b-if-works}
\=\+({\rm{boolp}}\,({\it{c\/}})\index{boolp} $\wedge$ {\rm{boolp}}\,({\it{a\/}})\index{boolp} $\wedge$ {\rm{boolp}}\,({\it{b\/}})\index{boolp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{b-if}}\,({\it{c\/}}, {\it{a\/}}, {\it{b\/}})\index{b-if} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{c\/}}$\;\;${\bf then }{\it{a\/}} \\ 
{\bf else }{\it{b\/}}$\;${\bf  endif}\-)\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Functions for composing the micro-processor                         ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{bv-reg-select} \\  
\=\+{\rm{bv-reg-select}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select} \\ 
$=$$\;\;\;\;${\rm{bv-if}}\,(\=\+{\rm{b-or}}\,({\it{reset\/}}, {\rm{b-pc-regnum}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-pc-regnum})\index{b-or}, \\ 
{\rm{nat-to-bv}}\,({\tt{0}}, {\tt{3}})\index{nat-to-bv}, \\ 
{\rm{bv-if}}\,(\=\+{\rm{b-oprda-oprdb}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-oprda-oprdb}, \\ 
{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b})\-\index{bv-if})\-\index{bv-if}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{bv-reg-select-with-ifs} \\  
\=\+{\rm{bv-reg-select-with-ifs}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-or}}\,({\it{reset\/}}, {\rm{b-pc-regnum}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-pc-regnum})\index{b-or}$\;\;${\bf then }{\rm{nat-to-bv}}\,({\tt{0}}, {\tt{3}})\index{nat-to-bv} \\ 
{\bf elseif }{\rm{b-oprda-oprdb}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-oprda-oprdb}$\;\;${\bf then }{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a} \\ 
{\bf else }{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-reg-select-ifs \\ \index{bv-reg-select-ifs}
{\rm{bv-reg-select}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select} $=$ {\rm{bv-reg-select-with-ifs}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select-with-ifs}
\end{tabbing}


\begin{tabbing}{\sc Definition}:\index{b-oprd-mem-ref} \\  
\=\+{\rm{b-oprd-mem-ref}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{b-oprd-mem-ref} \\ 
$=$$\;\;\;\;${\rm{b-if}}\,(\=\+{\rm{b-oprda-oprdb}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-oprda-oprdb}, \\ 
{\rm{b-not}}\,({\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a})\index{b-not}, \\ 
{\rm{b-not}}\,({\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})\index{b-not})\-\index{b-if}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-oprd-mem-ref-with-ifs} \\  
\=\+{\rm{b-oprd-mem-ref-with-ifs}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{b-oprd-mem-ref-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-oprda-oprdb}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-oprda-oprdb}$\;\;${\bf then }{\rm{b-not}}\,({\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a})\index{b-not} \\ 
{\bf else }{\rm{b-not}}\,({\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})\index{b-not}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  b-oprd-mem-ref-ifs \\ \index{b-oprd-mem-ref-ifs}
{\rm{b-oprd-mem-ref}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{b-oprd-mem-ref} $=$ {\rm{b-oprd-mem-ref-with-ifs}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{b-oprd-mem-ref-with-ifs}
\end{tabbing}


\noindent{\sc Event}:   Disable b-oprd-mem-ref.

\addvspace{18pt}        \begin{verbatim}; This disable was not here when FM8501 proved.

;  Next micro-address

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{mar} \\  
\=\+{\rm{mar}}\,({\it{mar\/}}, {\it{i-reg\/}}, {\it{dtack\/}}, {\it{reset\/}}, {\it{no-store\/}})\index{mar} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-or}}\,(\=\+{\rm{b-or}}\,({\it{reset\/}}, {\rm{b-or}}\,({\it{dtack\/}}, {\rm{b-seq}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-seq})\index{b-or})\index{b-or}, \\ 
{\rm{b-or}}\,(\=\+{\rm{b-and}}\,({\rm{b-en-no-store}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-en-no-store}, {\it{no-store\/}})\index{b-and}, \\ 
{\rm{b-and}}\,(\=\+{\rm{b-not}}\,({\rm{b-oprd-mem-ref}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{b-oprd-mem-ref})\index{b-not}, \\ 
{\rm{b-not}}\,({\rm{b-ir-mem-ref}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-ir-mem-ref})\index{b-not})\-\index{b-and})\-\index{b-or})\-\index{b-or}, \\ 
{\it{mar\/}}, \\ 
{\rm{bv-if}}\,({\it{reset\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, {\rm{bv-next}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{bv-next})\index{bv-if})\-\index{update-v}\-
\end{tabbing}

\begin{verbatim};  Read register

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{read} \\  
\=\+{\rm{read}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{read} \\ 
$=$$\;\;\;\;${\rm{b-and}}\,(\=\+{\rm{b-or}}\,({\rm{b-oprd-mem-ref}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{b-oprd-mem-ref}, {\rm{b-ir-mem-ref}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-ir-mem-ref})\index{b-or}, \\ 
{\rm{b-rd}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-rd})\-\index{b-and}\-
\end{tabbing}

\begin{verbatim};  Write register

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{write} \\  
\=\+{\rm{write}}\,({\it{mar\/}}, {\it{i-reg\/}}, {\it{no-store\/}})\index{write} \\ 
$=$$\;\;\;\;${\rm{b-and}}\,(\=\+{\rm{b-wr}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-wr}, \\ 
{\rm{b-and}}\,({\rm{b-oprd-mem-ref}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{b-oprd-mem-ref}, {\rm{b-not}}\,({\it{no-store\/}})\index{b-not})\index{b-and})\-\index{b-and}\-
\end{tabbing}

\begin{verbatim};  Data acknowledgement

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{dtack} \\  
{\rm{dtack}}\,({\it{current-oracle-entry\/}})\index{dtack} $=$ {\rm{fix-bool}}\,({\rm{car}}\,({\it{current-oracle-entry\/}}))\index{fix-bool}
\end{tabbing}

\begin{verbatim};  Reset function

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{reset} \\  
{\rm{reset}}\,({\it{current-oracle-entry\/}})\index{reset} $=$ {\rm{fix-bool}}\,({\rm{cadr}}\,({\it{current-oracle-entry\/}}))\index{fix-bool}
\end{tabbing}

\begin{verbatim};  No-store -- defines the flag which allows FM8501 to do conditional stores.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{no-store} \\  
\=\+{\rm{no-store}}\,({\it{no-store\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{no-store} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, \\ 
{\it{no-store\/}}, \\ 
{\rm{b-not}}\,({\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result})\index{b-not})\-\index{update-v}\-
\end{tabbing}


\begin{tabbing}{\sc Definition}:\index{no-store-with-ifs} \\  
\=\+{\rm{no-store-with-ifs}}\,({\it{no-store\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{no-store-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result} \\ 
{\bf then }$\neg$ {\rm{b-store-alu-result-with-ifs}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{i-reg\/}})\-\index{b-store-alu-result-with-ifs} \\ 
{\bf else }{\it{no-store\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  no-store-ifs \\ \index{no-store-ifs}
\=\+{\rm{no-store}}\,({\it{no-store\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{no-store} \\ 
$=$$\;\;\;\;${\rm{no-store-with-ifs}}\,({\it{no-store\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{no-store-with-ifs}\-
\end{tabbing}


\noindent{\sc Event}:   Disable no-store.

\addvspace{18pt}

\begin{verbatim};  Bit-vector result of the ALU

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{data-out} \\  
\=\+{\rm{data-out}}\,({\it{data-out\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{data-out} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, \\ 
{\it{data-out\/}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv})\-\index{update-v}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{data-out-with-ifs} \\  
\=\+{\rm{data-out-with-ifs}}\,({\it{data-out\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{data-out-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result} \\ 
{\bf then }{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv} \\ 
{\bf else }{\it{data-out\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  data-out-ifs \\ \index{data-out-ifs}
\=\+{\rm{data-out}}\,({\it{data-out\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{data-out} \\ 
$=$$\;\;\;\;${\rm{data-out-with-ifs}}\,({\it{data-out\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{data-out-with-ifs}\-
\end{tabbing}


\noindent{\sc Event}:   Disable data-out.

\addvspace{18pt}

\begin{verbatim};  Calculates the next value of the register file.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{reg-file} \\  
\=\+{\rm{reg-file}}\,({\it{reg-file\/}}, {\it{data-out\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{no-store\/}}, {\it{reset\/}})\index{reg-file} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-or}}\,(\=\+{\rm{b-or}}\,({\it{reset\/}}, {\rm{b-force-inc}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-force-inc})\index{b-or}, \\ 
{\rm{b-or}}\,(\=\+{\rm{b-or}}\,(\=\+{\rm{b-pc-regnum}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-pc-regnum}, \\ 
{\rm{b-and}}\,(\=\+{\rm{b-wr}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-wr}, \\ 
{\rm{b-and}}\,(\=\+{\rm{b-not}}\,({\it{no-store\/}})\index{b-not}, \\ 
{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})\-\index{b-and})\-\index{b-and})\-\index{b-or}, \\ 
{\rm{b-or}}\,(\=\+{\rm{b-and}}\,(\=\+{\rm{b-predec}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-predec}, \\ 
{\rm{b-if}}\,(\=\+{\rm{b-oprda-oprdb}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-oprda-oprdb}, \\ 
{\rm{b-indirect-reg-a-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-dec}, \\ 
{\rm{b-indirect-reg-b-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-dec})\-\index{b-if})\-\index{b-and}, \\ 
{\rm{b-and}}\,(\=\+{\rm{b-postinc}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-postinc}, \\ 
{\rm{b-if}}\,(\=\+{\rm{b-oprda-oprdb}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-oprda-oprdb}, \\ 
{\rm{b-indirect-reg-a-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-inc}, \\ 
{\rm{b-indirect-reg-b-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-inc})\-\index{b-if})\-\index{b-and})\-\index{b-or})\-\index{b-or})\-\index{b-or}, \\ 
{\rm{bv-reg-select}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{bv-if}}\,(\=\+{\rm{b-or}}\,({\rm{b-dout-incdec}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-dout-incdec}, {\it{reset\/}})\index{b-or}, \\ 
{\rm{bv-if}}\,({\it{reset\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv}, {\it{data-out\/}})\index{bv-if}, \\ 
{\rm{bv-if}}\,(\=\+{\rm{b-or}}\,(\=\+{\rm{b-force-inc}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-force-inc}, \\ 
{\rm{b-if}}\,(\=\+{\rm{b-oprda-oprdb}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-oprda-oprdb}, \\ 
{\rm{b-indirect-reg-a-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-inc}, \\ 
{\rm{b-indirect-reg-b-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-inc})\-\index{b-if})\-\index{b-or}, \\ 
{\rm{bv-adder-output}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv}, \\ 
{\rm{v-nth}}\,(\=\+{\rm{bv-reg-select}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{mar\/}}, \\ 
{\it{reset\/}})\-\index{bv-reg-select}, \\ 
{\it{reg-file\/}})\-\index{v-nth})\-\index{bv-adder-output}, \\ 
{\rm{bv-subtracter-output}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{nat-to-bv}, \\ 
{\rm{v-nth}}\,(\=\+{\rm{bv-reg-select}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{mar\/}}, \\ 
{\it{reset\/}})\-\index{bv-reg-select}, \\ 
{\it{reg-file\/}})\-\index{v-nth})\-\index{bv-subtracter-output})\-\index{bv-if})\-\index{bv-if})\-\index{update-v-nth}\-
\end{tabbing}

\begin{verbatim};  Defines the output address presented by FM8501.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{addr-out} \\  
\=\+{\rm{addr-out}}\,({\it{addr-out\/}}, {\it{reg-file\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{addr-out} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-we-addr-out}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-addr-out}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{bv-if}}\,(\=\+{\rm{b-and}}\,(\=\+{\rm{b-predec}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-predec}, \\ 
{\rm{b-if}}\,(\=\+{\rm{b-oprda-oprdb}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-oprda-oprdb}, \\ 
{\rm{b-indirect-reg-a-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-dec}, \\ 
{\rm{b-indirect-reg-b-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-dec})\-\index{b-if})\-\index{b-and}, \\ 
{\rm{bv-subtracter-output}}\,(\=\+{\bf{t}}, \\ 
{\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv}, \\ 
{\rm{v-nth}}\,(\=\+{\rm{bv-reg-select}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{mar\/}}, \\ 
{\it{reset\/}})\-\index{bv-reg-select}, \\ 
{\it{reg-file\/}})\-\index{v-nth})\-\index{bv-subtracter-output}, \\ 
{\rm{v-nth}}\,({\rm{bv-reg-select}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select}, {\it{reg-file\/}})\index{v-nth})\-\index{bv-if})\-\index{update-v}\-
\end{tabbing}

\begin{verbatim};  Carry flag

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{c-flag} \\  
\=\+{\rm{c-flag}}\,({\it{c-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{c-flag} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-and}}\,({\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, {\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set})\index{b-and}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{c})\-\index{update-v}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{c-flag-with-ifs} \\  
\=\+{\rm{c-flag-with-ifs}}\,({\it{c-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{c-flag-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-and}}\,({\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, {\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set})\index{b-and} \\ 
{\bf then }{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{c} \\ 
{\bf else }{\it{c-flag\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  c-flag-ifs \\ \index{c-flag-ifs}
\=\+{\rm{c-flag}}\,({\it{c-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{c-flag} \\ 
$=$$\;\;\;\;${\rm{c-flag-with-ifs}}\,({\it{c-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{c-flag-with-ifs}\-
\end{tabbing}


\noindent{\sc Event}:   Disable c-flag.

\addvspace{18pt}

\begin{verbatim};  The overflow flag

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{v-flag} \\  
\=\+{\rm{v-flag}}\,({\it{v-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{v-flag} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-and}}\,({\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, {\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set})\index{b-and}, \\ 
{\it{v-flag\/}}, \\ 
{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{v})\-\index{update-v}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{v-flag-with-ifs} \\  
\=\+{\rm{v-flag-with-ifs}}\,({\it{v-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{v-flag-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-and}}\,({\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, {\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set})\index{b-and} \\ 
{\bf then }{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{v} \\ 
{\bf else }{\it{v-flag\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  v-flag-ifs \\ \index{v-flag-ifs}
\=\+{\rm{v-flag}}\,({\it{v-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{v-flag} \\ 
$=$$\;\;\;\;${\rm{v-flag-with-ifs}}\,({\it{v-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{v-flag-with-ifs}\-
\end{tabbing}


\noindent{\sc Event}:   Disable v-flag.

\addvspace{18pt}

\begin{verbatim};  The zero flag

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{z-flag} \\  
\=\+{\rm{z-flag}}\,({\it{z-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{z-flag} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-and}}\,({\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, {\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set})\index{b-and}, \\ 
{\it{z-flag\/}}, \\ 
{\rm{b-bv-zerop}}\,({\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv})\index{b-bv-zerop})\-\index{update-v}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{z-flag-with-ifs} \\  
\=\+{\rm{z-flag-with-ifs}}\,({\it{z-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{z-flag-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-and}}\,({\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, {\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set})\index{b-and} \\ 
{\bf then }{\rm{b-bv-zerop}}\,({\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv})\index{b-bv-zerop} \\ 
{\bf else }{\it{z-flag\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  z-flag-ifs \\ \index{z-flag-ifs}
\=\+{\rm{z-flag}}\,({\it{z-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{z-flag} \\ 
$=$$\;\;\;\;${\rm{z-flag-with-ifs}}\,({\it{z-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{z-flag-with-ifs}\-
\end{tabbing}


\noindent{\sc Event}:   Disable z-flag.

\addvspace{18pt}

\begin{verbatim};  Two's complement negative flag

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{n-flag} \\  
\=\+{\rm{n-flag}}\,({\it{n-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{n-flag} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-and}}\,({\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, {\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set})\index{b-and}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{bitn}}\,(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{bitn})\-\index{update-v}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{n-flag-with-ifs} \\  
\=\+{\rm{n-flag-with-ifs}}\,({\it{n-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{n-flag-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-and}}\,({\rm{b-we-alu-result}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-alu-result}, {\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set})\index{b-and} \\ 
{\bf then }{\rm{bitn}}\,(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{bitn} \\ 
{\bf else }{\it{n-flag\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  n-flag-ifs \\ \index{n-flag-ifs}
\=\+{\rm{n-flag}}\,({\it{n-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{n-flag} \\ 
$=$$\;\;\;\;${\rm{n-flag-with-ifs}}\,({\it{n-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{n-flag-with-ifs}\-
\end{tabbing}


\noindent{\sc Event}:   Disable n-flag.

\addvspace{18pt}

\begin{verbatim};  Operand A for the ALU

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{a-reg} \\  
\=\+{\rm{a-reg}}\,({\it{a-reg\/}}, {\it{visual-mem\/}}, {\it{reg-file\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{a-reg} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-we-a-reg}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-a-reg}, \\ 
{\it{a-reg\/}}, \\ 
{\rm{bv-if}}\,(\=\+{\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a}, \\ 
{\rm{v-nth}}\,({\rm{bv-reg-select}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select}, {\it{reg-file\/}})\index{v-nth}, \\ 
{\it{visual-mem\/}})\-\index{bv-if})\-\index{update-v}\-
\end{tabbing}

\begin{verbatim};  Operand B for the ALU

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-reg} \\  
\=\+{\rm{b-reg}}\,({\it{b-reg\/}}, {\it{visual-mem\/}}, {\it{reg-file\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{b-reg} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-we-b-reg}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-b-reg}, \\ 
{\it{b-reg\/}}, \\ 
{\rm{bv-if}}\,(\=\+{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}, \\ 
{\rm{v-nth}}\,({\rm{bv-reg-select}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select}, {\it{reg-file\/}})\index{v-nth}, \\ 
{\it{visual-mem\/}})\-\index{bv-if})\-\index{update-v}\-
\end{tabbing}

\begin{verbatim};  Fills the instruction register

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{i-reg} \\  
\=\+{\rm{i-reg}}\,({\it{i-reg\/}}, {\it{visual-mem\/}}, {\it{mar\/}})\index{i-reg} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,({\rm{b-we-ir}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-ir}, {\it{i-reg\/}}, {\it{visual-mem\/}})\index{update-v}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{i-reg-with-ifs} \\  
\=\+{\rm{i-reg-with-ifs}}\,({\it{i-reg\/}}, {\it{visual-mem\/}}, {\it{mar\/}})\index{i-reg-with-ifs} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-we-ir}}\,({\rm{micro-rom}}\,({\it{mar\/}})\index{micro-rom})\index{b-we-ir}$\;\;${\bf then }{\it{visual-mem\/}} \\ 
{\bf else }{\it{i-reg\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  i-reg-ifs \\ \index{i-reg-ifs}
{\rm{i-reg}}\,({\it{i-reg\/}}, {\it{visual-mem\/}}, {\it{mar\/}})\index{i-reg} $=$ {\rm{i-reg-with-ifs}}\,({\it{i-reg\/}}, {\it{visual-mem\/}}, {\it{mar\/}})\index{i-reg-with-ifs}
\end{tabbing}


\noindent{\sc Event}:   Disable i-reg.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Memory process                                                      ;;
;;                                                                              ;;
;;          The memory process is interesting as it requires history to         ;;
;;          operate.  VISUAL-MEM is the description of how a memory that        ;;
;;          FM8501 reads is expected to act.  A "correct" memory value is       ;;
;;          only returned after the READ line has been on for two clock "ticks",;;
;;          the WRITE line is off, DTACK is on, RESET is off, and DATA-OUT      ;;
;;          and ADDR-OUT have been stable for two clock "ticks".  VISUAL-MEM    ;;
;;          embodies the assumptions made about reading memory.  REAL-MEM       ;;
;;          is a function that actually updates the memory.  Its assumptions    ;;
;;          are expressed similarily as VISUAL-MEM.  The WATCH-DOG allows       ;;
;;          one tick's worth of state to be kept concerning READ, WRITE,        ;;
;;          DTACK, DATA-OUT, and ADDR-OUT.                                      ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}
\noindent{\sc Event}:   Add the shell {\it{watch-dog\/}}\index{watch-dog}, with recognizer function symbol {\it{watch-dogp\/}} and 5 accessors: {\it{read-1\/}}, with type restriction (none-of) and default value false; {\it{write-1\/}}, with type restriction (none-of) and default value false; {\it{dtack-1-oracle\/}}, with type restriction (none-of) and default value false; {\it{data-out-1\/}}, with type restriction (one-of bitvp) and default value btm; {\it{addr-out-1\/}}, with type restriction (one-of bitvp) and default value btm.

\addvspace{18pt}



\noindent{\sc Event}:   Introduce the function symbol {\it default-visual-mem-value\index{default-visual-mem-value}\/} of 0 arguments.

\addvspace{18pt}       \begin{verbatim}; Default value from memory when memory
                                        ; has not been selected to return a value.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{visual-mem} \\  
\=\+{\rm{visual-mem}}\,(\=\+{\it{real-mem\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\it{dtack-oracle\/}}, \\ 
{\it{reset-oracle\/}})\-\index{visual-mem} \\ 
$=$$\;\;\;\;${\rm{trunc}}\,(\=\+\=\+{\bf if }\=\+({\it{read\/}} $\wedge$ {\rm{read-1}}\,({\it{memory-watch-dog-history\/}})\index{read-1}) \\ 
$\wedge$$\;\;\;\;$(\=\+($\neg$ {\it{write\/}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{write-1}}\,({\it{memory-watch-dog-history\/}})\index{write-1}))\- \\ 
$\wedge$$\;\;\;\;$({\it{addr-out\/}} $=$ {\rm{addr-out-1}}\,({\it{memory-watch-dog-history\/}})\index{addr-out-1}) \\ 
$\wedge$$\;\;\;\;$({\it{dtack-oracle\/}} $\wedge$ {\rm{dtack-1-oracle}}\,({\it{memory-watch-dog-history\/}})\index{dtack-1-oracle}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\it{reset-oracle\/}})\-$\;\;${\bf then }{\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth} \\ 
{\bf else }{\sc{default-visual-mem-value}}\index{default-visual-mem-value}$\;${\bf  endif}\-, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{trunc}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{real-mem} \\  
\=\+{\rm{real-mem}}\,(\=\+{\it{real-mem\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\it{dtack-oracle\/}}, \\ 
{\it{reset-oracle\/}})\-\index{real-mem} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+\=\+({\it{write\/}} $\wedge$ {\rm{write-1}}\,({\it{memory-watch-dog-history\/}})\index{write-1}) \\ 
$\wedge$$\;\;\;\;$(\=\+($\neg$ {\it{read\/}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{read-1}}\,({\it{memory-watch-dog-history\/}})\index{read-1}))\- \\ 
$\wedge$$\;\;\;\;$({\it{addr-out\/}} $=$ {\rm{addr-out-1}}\,({\it{memory-watch-dog-history\/}})\index{addr-out-1}) \\ 
$\wedge$$\;\;\;\;$({\it{dtack-oracle\/}} $\wedge$ ($\neg$ {\rm{dtack-1-oracle}}\,({\it{memory-watch-dog-history\/}})\index{dtack-1-oracle})) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\it{reset-oracle\/}})\-, \\ 
{\it{addr-out\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{data-out\/}})\-\index{update-v-nth}\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          "big-machine" -- the definition of the microprocessor               ;;
;;                                                                              ;;
;;          This function is the definition of the FM8501 microprocessor.       ;;
;;          BIG-MACHINE executes as along as there are clock "ticks".  Clock    ;;
;;          "ticks" are characterized by there being elements left in the       ;;
;;          ORACLE.  Otherwise, this function just stops, effectively           ;;
;;          freezing the value of its variables (registers).                    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{big-machine} \\  
\=\+{\rm{big-machine}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\it{oracle\/}})\-\index{big-machine} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{oracle\/}} $\simeq\;${{\bf{nil}}}${}$ \\ 
{\bf then }{\rm{list}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}})\- \\ 
{\bf else }{\rm{big-machine}}\,(\=\+{\rm{mar}}\,({\it{mar\/}}, {\it{i-reg\/}}, {\it{dtack\/}}, {\it{reset\/}}, {\it{no-store\/}})\index{mar}, \\ 
{\rm{read}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{read}, \\ 
{\rm{write}}\,({\it{mar\/}}, {\it{i-reg\/}}, {\it{no-store\/}})\index{write}, \\ 
{\rm{dtack}}\,({\rm{car}}\,({\it{oracle\/}}))\index{dtack}, \\ 
{\rm{reset}}\,({\rm{car}}\,({\it{oracle\/}}))\index{reset}, \\ 
{\rm{no-store}}\,(\=\+{\it{no-store\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}})\-\index{no-store}, \\ 
{\rm{data-out}}\,({\it{data-out\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{data-out}, \\ 
{\rm{reg-file}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{reset\/}})\-\index{reg-file}, \\ 
{\rm{addr-out}}\,({\it{addr-out\/}}, {\it{reg-file\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{addr-out}, \\ 
{\rm{c-flag}}\,({\it{c-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{c-flag}, \\ 
{\rm{v-flag}}\,({\it{v-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{v-flag}, \\ 
{\rm{z-flag}}\,({\it{z-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{z-flag}, \\ 
{\rm{n-flag}}\,({\it{n-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{n-flag}, \\ 
{\rm{a-reg}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}}, \\ 
{\it{reset\/}})\-\index{a-reg}, \\ 
{\rm{b-reg}}\,(\=\+{\it{b-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}}, \\ 
{\it{reset\/}})\-\index{b-reg}, \\ 
{\rm{i-reg}}\,({\it{i-reg\/}}, {\it{visual-mem\/}}, {\it{mar\/}})\index{i-reg}, \\ 
{\rm{visual-mem}}\,(\=\+{\it{real-mem\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{dtack}}\,({\rm{car}}\,({\it{oracle\/}}))\index{dtack}, \\ 
{\rm{reset}}\,({\rm{car}}\,({\it{oracle\/}}))\index{reset})\-\index{visual-mem}, \\ 
{\rm{real-mem}}\,(\=\+{\it{real-mem\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{dtack}}\,({\rm{car}}\,({\it{oracle\/}}))\index{dtack}, \\ 
{\rm{reset}}\,({\rm{car}}\,({\it{oracle\/}}))\index{reset})\-\index{real-mem}, \\ 
{\rm{watch-dog}}\,(\=\+{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\rm{dtack}}\,({\rm{car}}\,({\it{oracle\/}}))\index{dtack}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}})\-\index{watch-dog}, \\ 
{\rm{cdr}}\,({\it{oracle\/}}))\-\index{big-machine}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          "big-machine" operation on lists and empty lists                    ;;
;;                                                                              ;;
;;          The following two lemmas describe what BIG-MACHINE does when        ;;
;;          clock "ticks" are available or the clock has been exhausted.        ;;
;;          This information is easily available by looking at the definition   ;;
;;          BIG-MACHINE; however, these formulations make it easier for the     ;;
;;          theorem-prover to reason about BIG-MACHINE.                         ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  open-big-machine-on-nlistp \\ \index{open-big-machine-on-nlistp}
\=\+($\neg$ {\rm{listp}}\,({\it{oracle\/}})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\it{oracle\/}})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  open-big-machine-on-listp \\ \index{open-big-machine-on-listp}
\=\+{\rm{listp}}\,({\it{oracle\/}}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\it{oracle\/}})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{big-machine}}\,(\=\+{\rm{mar}}\,({\it{mar\/}}, {\it{i-reg\/}}, {\it{dtack\/}}, {\it{reset\/}}, {\it{no-store\/}})\index{mar}, \\ 
{\rm{read}}\,({\it{mar\/}}, {\it{i-reg\/}})\index{read}, \\ 
{\rm{write}}\,({\it{mar\/}}, {\it{i-reg\/}}, {\it{no-store\/}})\index{write}, \\ 
{\rm{dtack}}\,({\rm{car}}\,({\it{oracle\/}}))\index{dtack}, \\ 
{\rm{reset}}\,({\rm{car}}\,({\it{oracle\/}}))\index{reset}, \\ 
{\rm{no-store-with-ifs}}\,(\=\+{\it{no-store\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}})\-\index{no-store-with-ifs}, \\ 
{\rm{data-out-with-ifs}}\,(\=\+{\it{data-out\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}})\-\index{data-out-with-ifs}, \\ 
{\rm{reg-file}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{reset\/}})\-\index{reg-file}, \\ 
{\rm{addr-out}}\,({\it{addr-out\/}}, {\it{reg-file\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{addr-out}, \\ 
{\rm{c-flag-with-ifs}}\,({\it{c-flag\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{i-reg\/}}, {\it{mar\/}})\index{c-flag-with-ifs}, \\ 
{\rm{v-flag-with-ifs}}\,(\=\+{\it{v-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}})\-\index{v-flag-with-ifs}, \\ 
{\rm{z-flag-with-ifs}}\,(\=\+{\it{z-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}})\-\index{z-flag-with-ifs}, \\ 
{\rm{n-flag-with-ifs}}\,(\=\+{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{mar\/}})\-\index{n-flag-with-ifs}, \\ 
{\rm{a-reg}}\,({\it{a-reg\/}}, {\it{visual-mem\/}}, {\it{reg-file\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{a-reg}, \\ 
{\rm{b-reg}}\,({\it{b-reg\/}}, {\it{visual-mem\/}}, {\it{reg-file\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{b-reg}, \\ 
{\rm{i-reg-with-ifs}}\,({\it{i-reg\/}}, {\it{visual-mem\/}}, {\it{mar\/}})\index{i-reg-with-ifs}, \\ 
{\rm{visual-mem}}\,(\=\+{\it{real-mem\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{dtack}}\,({\rm{car}}\,({\it{oracle\/}}))\index{dtack}, \\ 
{\rm{reset}}\,({\rm{car}}\,({\it{oracle\/}}))\index{reset})\-\index{visual-mem}, \\ 
{\rm{real-mem}}\,(\=\+{\it{real-mem\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{dtack}}\,({\rm{car}}\,({\it{oracle\/}}))\index{dtack}, \\ 
{\rm{reset}}\,({\rm{car}}\,({\it{oracle\/}}))\index{reset})\-\index{real-mem}, \\ 
{\rm{watch-dog}}\,(\=\+{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\rm{dtack}}\,({\rm{car}}\,({\it{oracle\/}}))\index{dtack}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}})\-\index{watch-dog}, \\ 
{\rm{cdr}}\,({\it{oracle\/}}))\-\index{big-machine})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable big-machine.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          This file contains definitions and lemmas concerning the            ;;
;;          sequencing of big-machine.  The proofs for the correctness of       ;;
;;          the micro-code are given here.                                      ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;




;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Lemma used to tear apart "append"ed oracles                         ;;
;;          This is the fundamental lemma for sequencing big-machine.           ;;
;;          It permits us to express computations on a (append a b) in terms    ;;
;;          of a computation on b applied to the state produced by a.  We can   ;;
;;          then get results about long computations by composing them from     ;;
;;          simple ones.                                                        ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;



\end{verbatim}\begin{tabbing}{\sc Theorem}:  big-machine-append \\ \index{big-machine-append}
\=\+({\it{m\/}} $=$ {\rm{big-machine}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\it{oracle1\/}})\-\index{big-machine}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{append}}\,({\it{oracle1\/}}, {\it{oracle2\/}}))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{big-machine}}\,(\=\+{\rm{car}}\,({\it{m\/}}), \\ 
{\rm{cadr}}\,({\it{m\/}}), \\ 
{\rm{caddr}}\,({\it{m\/}}), \\ 
{\rm{cadddr}}\,({\it{m\/}}), \\ 
{\rm{caddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddddddddddddddr}}\,({\it{m\/}}), \\ 
{\it{oracle2\/}})\-\index{big-machine})\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Miscellaneous lemmas about inc/dec and updating                     ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  bv-incrementer-truncates-to-machine-size \\ \index{bv-incrementer-truncates-to-mac!hine-size}
\=\+(\=\+({\it{zero\/}} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{bit-vec\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{bit-vec\/}})\index{size} $=$ {\sc{machine-size}}\index{machine-size}))\- \\ 
$\rightarrow$$\;\;\;\;$({\rm{bv-adder-output}}\,({\bf{t}}, {\it{zero\/}}, {\it{bit-vec\/}})\index{bv-adder-output} $=$ {\rm{v-nat-inc}}\,({\it{bit-vec\/}})\index{v-nat-inc})\-
\end{tabbing}


\noindent{\sc Event}:   Disable bv-incrementer-truncates-to-machine-size.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  bv-decrementer-truncates-to-machine-size-help \\ \index{bv-decrementer-truncates-to-mac!hine-size-help}
\=\+(\=\+({\rm{bv-to-nat}}\,({\it{bit-vec\/}})\index{bv-to-nat} $\not<$ {\tt{1}}) \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{bit-vec\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{bit-vec\/}})\index{size} $=$ {\tt{16}}) \\ 
$\wedge$$\;\;\;\;$({\rm{bv-to-nat}}\,({\it{bit-vec\/}})\index{bv-to-nat} $\not=$ {\tt{0}}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{bit-vec\/}})\index{bv-to-nat} $-$ {\tt{1}}, {\tt{16}})\index{nat-to-bv} \\ 
$=$$\;\;\;\;${\rm{nat-to-bv}}\,({\rm{bv-to-nat}}\,({\it{bit-vec\/}})\index{bv-to-nat} $-\;1$, {\tt{16}})\index{nat-to-bv})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  bv-decrementer-truncates-to-machine-size \\ \index{bv-decrementer-truncates-to-mac!hine-size}
\=\+(\=\+({\it{zero\/}} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{bitvp}}\,({\it{bit-vec\/}})\index{bitvp} \\ 
$\wedge$$\;\;\;\;$({\rm{size}}\,({\it{bit-vec\/}})\index{size} $=$ {\sc{machine-size}}\index{machine-size}))\- \\ 
$\rightarrow$$\;\;\;\;$({\rm{bv-subtracter-output}}\,({\bf{t}}, {\it{zero\/}}, {\it{bit-vec\/}})\index{bv-subtracter-output} $=$ {\rm{v-nat-dec}}\,({\it{bit-vec\/}})\index{v-nat-dec})\-
\end{tabbing}


\noindent{\sc Event}:   Disable bv-decrementer-truncates-to-machine-size-help.

\addvspace{18pt}

\noindent{\sc Event}:   Disable bv-decrementer-truncates-to-machine-size.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  trunc-size-1 \\ \index{trunc-size-1}
\=\+({\it{n\/}} $=$ {\rm{size}}\,({\it{a\/}})\index{size}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{trunc}}\,({\it{a\/}}, {\it{n\/}})\index{trunc} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{bitvp}}\,({\it{a\/}})\index{bitvp}$\;\;${\bf then }{\it{a\/}} \\ 
{\bf else }{\sc{btm}}\index{btm}$\;${\bf  endif}\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-v-nth \\ \index{size-v-nth}
\=\+(\=\+({\rm{size}}\,({\it{a\/}})\index{size} $=$ {\tt{3}}) \\ 
$\wedge$$\;\;\;\;$({\rm{length}}\,({\it{reg-file\/}})\index{length} $=$ {\tt{8}}) \\ 
$\wedge$$\;\;\;\;${\rm{every-member-sizep}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size})\index{every-member-sizep})\- \\ 
$\rightarrow$$\;\;\;\;$({\rm{size}}\,({\rm{v-nth}}\,({\it{a\/}}, {\it{reg-file\/}})\index{v-nth})\index{size} $=$ {\sc{machine-size}}\index{machine-size})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  update-update-nth \\ \index{update-update-nth}
\=\+{\rm{update-nth}}\,({\it{c\/}}, {\it{n\/}}, {\rm{update-nth}}\,({\it{c\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{value2\/}})\index{update-nth}, {\it{value1\/}})\index{update-nth} \\ 
$=$$\;\;\;\;${\rm{update-nth}}\,({\it{c\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{value1\/}})\index{update-nth}\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Resetting "big-machine"                                              ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  mar-on-reset \\ \index{mar-on-reset}
{\rm{mar}}\,({\it{mar\/}}, {\it{i-reg\/}}, {\it{dtack\/}}, {\bf{t}}, {\it{no-store\/}})\index{mar} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  reg-file-on-reset \\ \index{reg-file-on-reset}
\=\+{\rm{reg-file}}\,({\it{reg-file\/}}, {\it{data-out\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{no-store\/}}, {\bf{t}})\index{reg-file} \\ 
$=$$\;\;\;\;${\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv})\index{update-nth}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  listp-reg-file \\ \index{listp-reg-file}
\=\+{\rm{listp}}\,({\rm{reg-file}}\,({\it{reg-file\/}}, {\it{data-out\/}}, {\it{i-reg\/}}, {\it{mar\/}}, {\it{no-store\/}}, {\it{reset\/}})\index{reg-file}) \\ 
$=$$\;\;\;\;${\rm{listp}}\,({\it{reg-file\/}})\-
\end{tabbing}

\begin{verbatim};  The following lemma describes the first three clock "ticks" after a
;  reset occurs.  The memory-address register (MAR) is set to zero, the
;  read and write outputs are set to "false", and the reset latch is set
;  to "true".  Since nothing is know about the WATCH-DOG-HISTORY, it is
;  not possible to characterize what the memory state is.  However, after
;  these three clock "ticks" everything is stable (unchanging) until reset
;  is turned off.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  reset-to-state-0 \\ \index{reset-to-state-0}
\=\+(\=\+{\rm{standard-hyps}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}})\-\index{standard-hyps} \\ 
$\wedge$$\;\;\;\;$({\it{m\/}} $=$ {\rm{big-machine}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\it{dt1\/}}, {\bf{t}}), {\rm{list}}\,({\it{dt2\/}}, {\bf{t}}), {\rm{list}}\,({\it{dt3\/}}, {\bf{t}})))\-\index{big-machine}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+({\rm{car}}\,({\it{m\/}}) $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;$({\rm{cadr}}\,({\it{m\/}}) $=$ {\bf{f}}) \\ 
$\wedge$$\;\;\;\;$({\rm{caddr}}\,({\it{m\/}}) $=$ {\bf{f}}) \\ 
$\wedge$$\;\;\;\;$({\rm{caddddr}}\,({\it{m\/}}) $=$ {\bf{t}}) \\ 
$\wedge$$\;\;\;\;$({\rm{nth}}\,({\tt{0}}, {\rm{cadddddddr}}\,({\it{m\/}}))\index{nth} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv}))\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable reset-to-state-0.

\addvspace{18pt}

\begin{tabbing}{\sc Definition}:\index{list-of-n-plus-1-dtack-off-reset!-on} \\  
\=\+{\rm{list-of-n-plus-1-dtack-off-reset-on}}\,({\it{count\/}})\index{list-of-n-plus-1-dtack-off-reset!-on} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{count\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{t}})) \\ 
{\bf else }{\rm{cons}}\,(\=\+{\rm{list}}\,({\bf{f}}, {\bf{t}}), \\ 
{\rm{list-of-n-plus-1-dtack-off-reset-on}}\,({\it{count\/}} $-\;1$)\index{list-of-n-plus-1-dtack-off-reset!-on})\-$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-0-to-0-wait-help \\ \index{state-0-to-0-wait-help}
\=\+({\it{mar0\/}} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar0\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{cons}}\,({\rm{list}}\,({\it{dt-any\/}}, {\bf{t}}), {\it{oracle\/}}))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{big-machine}}\,(\=\+{\it{mar0\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\rm{fix-bool}}\,({\it{dt-any\/}})\index{fix-bool}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv})\-\index{update-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\rm{fix-bool}}\,({\it{dt-any\/}})\index{fix-bool}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\it{oracle\/}})\-\index{big-machine})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-0-to-0-wait-help.

\addvspace{18pt}

\begin{tabbing}{\sc Definition}:\index{state-0-to-0-induction} \\  
\=\+{\rm{state-0-to-0-induction}}\,(\=\+{\it{dtack\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\it{n\/}})\-\index{state-0-to-0-induction} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\rm{state-0-to-0-induction}}\,(\=\+{\bf{f}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{nat-to-bv}}\,(\=\+{\tt{0}}, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{nat-to-bv})\-\index{update-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{trunc}}\,(\=\+{\sc{default-visual-mem-value}}\index{default-visual-mem-value}, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{trunc}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\it{n\/}} $-\;1$)\-\index{state-0-to-0-induction}$\;${\bf  endif}\-\-
\end{tabbing}
                       
\begin{tabbing}{\sc Theorem}:  state-0-to-0-wait \\ \index{state-0-to-0-wait}
\=\+({\it{mar0\/}} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar0\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list-of-n-plus-1-dtack-off-reset-on}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-off-reset!-on})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv})\index{update-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-0-to-0-wait.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-0-to-1 \\ \index{state-0-to-1}
\=\+({\it{mar0\/}} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar0\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\it{dt-any1\/}}, {\bf{f}}), {\rm{list}}\,({\it{dt-any2\/}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\rm{fix-bool}}\,({\it{dt-any2\/}})\index{fix-bool}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv})\index{update-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\rm{fix-bool}}\,({\it{dt-any2\/}})\index{fix-bool}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-0-to-1.

\addvspace{18pt}

\begin{tabbing}{\sc Definition}:\index{state-0-to-0-wait-to-1-oracle} \\  
\=\+{\rm{state-0-to-0-wait-to-1-oracle}}\,({\it{n\/}})\index{state-0-to-0-wait-to-1-oracle} \\ 
$=$$\;\;\;\;${\rm{append}}\,(\=\+{\rm{list-of-n-plus-1-dtack-off-reset-on}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-off-reset!-on}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\-
\end{tabbing}

\begin{verbatim};  After the MAR has been set to zero, this lemma describes the steps taken by
;  FM8501 to prepare itself for executing instructions.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-0-to-0-wait-to-1 \\ \index{state-0-to-0-wait-to-1}
\=\+(\=\+{\rm{standard-hyps}}\,(\=\+{\it{mar0\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}})\-\index{standard-hyps} \\ 
$\wedge$$\;\;\;\;$({\it{mar0\/}} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar0\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{state-0-to-0-wait-to-1-oracle}}\,({\it{n\/}})\index{state-0-to-0-wait-to-1-oracle})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv})\index{update-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-0-to-0-wait-to-1.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          "big-machine" instruction loop -- micro-state by micro-state        ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Fetch the instruction, and increment the PC                         ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; We are about to embark on a litany of lemmas that move us from one microcode
; state to another.  By inspection of the oracles used below one can deduce the
; timing diagrams.  For example, the lemma below moves us from microcode state 
; 1, where mar=1, and read, write, and reset are f, to microcode state 2, where
; mar=2, read, write, dtack and reset are f, the pc has been incremented,
; and addr-out contains the old pc.  To move from state 1 to 2, we need
; one clock tick with both dtack and reset f.

; We will similarly move through every state, some of which have several
; substates as we set lines, wait for acknowledgment, and then move.
; Once we get all the way through the microcode, we will append together
; the oracles to get an oracle that moves us all the way around from state 1
; to state 1.

; These lemmas make it perfectly clear what each state in the microcode does
; and how long each takes.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-1-to-2 \\ \index{state-1-to-2}
\=\+({\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} $\wedge$ ({\it{mar1\/}} $=$ {\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar1\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{v-nat-inc}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{v-nat-inc})\index{update-nth}, \\ 
{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-1-to-2.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-2-to-3-init \\ \index{state-2-to-3-init}
\=\+({\it{mar2\/}} $=$ {\rm{nat-to-bv}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar2\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{list-of-n-plus-1-dtack-reset-of!f} \\  
\=\+{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{count\/}})\index{list-of-n-plus-1-dtack-reset-of!f} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{count\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})) \\ 
{\bf else }{\rm{cons}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{count\/}} $-\;1$)\index{list-of-n-plus-1-dtack-reset-of!f})$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-2-to-2-wait-help \\ \index{state-2-to-2-wait-help}
\=\+({\it{mar2\/}} $=$ {\rm{nat-to-bv}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar2\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{cons}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\it{oracle\/}}))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{big-machine}}\,(\=\+{\it{mar2\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\it{oracle\/}})\-\index{big-machine})\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{state-2-to-2-induction} \\  
\=\+{\rm{state-2-to-2-induction}}\,(\=\+{\it{dtack\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\it{n\/}})\-\index{state-2-to-2-induction} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\rm{state-2-to-2-induction}}\,(\=\+{\bf{f}}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{trunc}}\,(\=\+{\sc{default-visual-mem-value}}\index{default-visual-mem-value}, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{trunc}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\it{n\/}} $-\;1$)\-\index{state-2-to-2-induction}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-2-to-3-wait \\ \index{state-2-to-3-wait}
\=\+({\it{mar2\/}} $=$ {\rm{nat-to-bv}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar2\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-2-to-3-wait.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  upper-bound-bridge \\ \index{upper-bound-bridge}
({\it{n\/}} $=$ {\rm{exp}}\,({\tt{2}}, {\rm{size}}\,({\it{a\/}})\index{size})\index{exp}) $\rightarrow$ ({\rm{bv-to-nat}}\,({\it{a\/}})\index{bv-to-nat} $<$ {\it{n\/}})
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-2-to-3-step3 \\ \index{state-2-to-3-step3}
\=\+(\=\+{\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$({\it{mar2\/}} $=$ {\rm{nat-to-bv}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;$({\it{visual-mem\/}} $=$ {\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar2\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{3}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-2-to-3-step3.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  state-3-to-4 \\ \index{state-3-to-4}
\=\+(\=\+{\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$({\it{mar3\/}} $=$ {\rm{nat-to-bv}}\,({\tt{3}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;$({\it{visual-mem\/}} $=$ {\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar3\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{4}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-3-to-4.

\addvspace{18pt}

\begin{verbatim};  This proof is required because it is impossible to keep "APPEND"
;  from opening up on constants.  The opening does not allow 
;  "BIG-MACHINE-APPEND" to apply because the 'append' will have
;  disappeared before it get a chance to apply.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-2-to-3-step3-to-4 \\ \index{state-2-to-3-step3-to-4}
\=\+(\=\+{\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$({\it{mar2\/}} $=$ {\rm{nat-to-bv}}\,({\tt{2}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar2\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{4}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-2-to-3-step3-to-4.

\addvspace{18pt}

\begin{tabbing}{\sc Definition}:\index{fetch-ir-oracle} \\  
\=\+{\rm{fetch-ir-oracle}}\,({\it{n\/}})\index{fetch-ir-oracle} \\ 
$=$$\;\;\;\;${\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-)\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-1-to-4 \\ \index{state-1-to-4}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar1\/}} $=$ {\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar1\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{fetch-ir-oracle}}\,({\it{n\/}})\index{fetch-ir-oracle})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{4}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{v-nat-inc}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{v-nat-inc})\index{update-nth}, \\ 
{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-1-to-4.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Some size lemmas                                                    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  size-bv-reg-select \\ \index{size-bv-reg-select}
{\rm{size}}\,({\rm{bv-reg-select}}\,({\it{i-reg\/}}, {\it{mar\/}}, {\it{reset\/}})\index{bv-reg-select})\index{size} $=$ {\tt{3}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-bv-oprd-a \\ \index{size-bv-oprd-a}
{\rm{size}}\,({\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a})\index{size} $=$ {\tt{3}}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-bv-oprd-b \\ \index{size-bv-oprd-b}
{\rm{size}}\,({\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b})\index{size} $=$ {\tt{3}}
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Fetch operand A, doing pre-decrement if necessary                   ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{fetch-oprd-a-reg-file} \\  
\=\+{\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-a-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-dec}, \\ 
{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-dec}}\,({\rm{v-nth}}\,({\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, {\it{reg-file\/}})\index{v-nth})\index{v-nat-dec})\-\index{update-v-nth}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  every-member-sizep-update-nth \\ \index{every-member-sizep-update-nth}
\=\+(({\rm{size}}\,({\it{x\/}})\index{size} $=$ {\it{width\/}}) $\wedge$ {\rm{every-member-sizep}}\,({\it{lst\/}}, {\it{width\/}})\index{every-member-sizep}) \\ 
$\rightarrow$$\;\;\;\;${\rm{every-member-sizep}}\,({\rm{update-nth}}\,({\it{bool\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{x\/}})\index{update-nth}, {\it{width\/}})\index{every-member-sizep}\-
\end{tabbing}

\begin{verbatim};  Both of the following two lemmas are needed, as we sometimes have RAMP enabled.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  ramp-fetch-oprd-a-reg-file \\ \index{ramp-fetch-oprd-a-reg-file}
\=\+(({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) $\wedge$ {\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+({\rm{length}}\,({\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file})\index{length} $=$ {\tt{8}}) \\ 
$\wedge$$\;\;\;\;${\rm{every-member-sizep}}\,({\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file}, {\it{m\/}})\index{every-member-sizep})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-fetch-oprd-a-reg-file-2 \\ \index{ramp-fetch-oprd-a-reg-file-2}
\=\+(({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) $\wedge$ {\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp}) \\ 
$\rightarrow$$\;\;\;\;${\rm{ramp}}\,({\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file}, {\it{m\/}}, {\tt{8}})\index{ramp}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{fetch-oprd-a-addr-out} \\  
\=\+{\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-indirect-reg-a-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-dec} \\ 
{\bf then }{\rm{v-nat-dec}}\,({\rm{v-nth}}\,({\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, {\it{reg-file\/}})\index{v-nth})\index{v-nat-dec} \\ 
{\bf else }{\rm{v-nth}}\,({\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, {\it{reg-file\/}})\index{v-nth}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  sizep-fetch-oprd-a-addr-out \\ \index{sizep-fetch-oprd-a-addr-out}
\=\+(({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) $\wedge$ {\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp}) \\ 
$\rightarrow$$\;\;\;\;$({\rm{size}}\,({\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out})\index{size} $=$ {\it{m\/}})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-4-to-5 \\ \index{state-4-to-5}
\=\+({\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} $\wedge$ ({\it{mar4\/}} $=$ {\rm{nat-to-bv}}\,({\tt{4}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar4\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file}, \\ 
{\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-4-to-5.

\addvspace{18pt}

\begin{verbatim};  The next two prove-lemmas are of type nil -- we never use them as
;  rewrite rules.  Ideally we would like to append together the two clocks
;  for state-5-to-6-reg and state-6-to-7-reg.  But the two clocks are both
;  constant so the append computes and big-machine-append will not apply.
;  So we will actually prove state-4-to-5-to-6-to-7-reg as one rewrite rule.
;  But for the sake of exposition, we prove individual lemmas about each
;  state transition.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-5-to-6-reg \\ \index{state-5-to-6-reg}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar5\/}} $=$ {\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar5\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dt-any\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{6}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-6-to-7-reg \\ \index{state-6-to-7-reg}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar6\/}} $=$ {\rm{nat-to-bv}}\,({\tt{6}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar6\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{7}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{v-nth}}\,({\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, {\it{reg-file\/}})\index{v-nth}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-5-to-6-mem-init \\ \index{state-5-to-6-mem-init}
\=\+(({\it{mar5\/}} $=$ {\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) $\wedge$ ($\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar5\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-5-to-6-mem-init.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-5-to-6-mem-help \\ \index{state-5-to-6-mem-help}
\=\+(({\it{mar5\/}} $=$ {\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) $\wedge$ ($\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar5\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{cons}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\it{oracle\/}}))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{big-machine}}\,(\=\+{\it{mar5\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\it{oracle\/}})\-\index{big-machine})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-5-to-6-mem-help.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-5-to-6-mem-wait \\ \index{state-5-to-6-mem-wait}
\=\+(({\it{mar5\/}} $=$ {\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) $\wedge$ ($\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar5\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-5-to-6-mem-wait.

\addvspace{18pt}


\begin{verbatim}; The next two lemmas we never use as rewrite rules, for the same reasons
; explained above.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-5-to-6-mem-dtack \\ \index{state-5-to-6-mem-dtack}
\=\+(\=\+({\it{mar5\/}} $=$ {\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar5\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{6}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-6-to-7-mem \\ \index{state-6-to-7-mem}
\=\+(\=\+({\it{mar6\/}} $=$ {\rm{nat-to-bv}}\,({\tt{6}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{visual-mem\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar6\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{7}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\begin{verbatim}; We now piece together states 4, 5, 6, and 7 for the reg case:

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-4-to-5-to-6-to-7-reg \\ \index{state-4-to-5-to-6-to-7-reg}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar4\/}} $=$ {\rm{nat-to-bv}}\,({\tt{4}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar4\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{7}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file}, \\ 
{\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file})\-\index{v-nth}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-4-to-5-to-6-to-7-reg.

\addvspace{18pt}


\begin{verbatim}; and now we do the same thing for 5, 6, and 7 in the mem case:

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-5-to-6-to-7-mem-dtack \\ \index{state-5-to-6-to-7-mem-dtack}
\=\+(\=\+({\it{mar5\/}} $=$ {\rm{nat-to-bv}}\,({\tt{5}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar5\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{7}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{trunc}}\,({\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-5-to-6-to-7-mem-dtack.

\addvspace{18pt}


\begin{verbatim}; Finally, we do the entire transition from state 4 to state 7.  We first
; define the oracle necessary to drive the machine through the sequence.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{fetch-oprd-a-oracle} \\  
\=\+{\rm{fetch-oprd-a-oracle}}\,({\it{i-reg\/}}, {\it{n\/}})\index{fetch-oprd-a-oracle} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a}$\;\;${\bf then }{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})) \\ 
{\bf else }{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-)\-)\-$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  every-member-sizep-update-nth-machine-size \\ \index{every-member-sizep-update-nth-m!achine-size}
\=\+(({\rm{size}}\,({\it{x\/}})\index{size} $=$ {\tt{16}}) $\wedge$ {\rm{every-member-sizep}}\,({\it{lst\/}}, {\tt{16}})\index{every-member-sizep}) \\ 
$\rightarrow$$\;\;\;\;${\rm{every-member-sizep}}\,({\rm{update-nth}}\,({\it{bool\/}}, {\it{n\/}}, {\it{lst\/}}, {\it{x\/}})\index{update-nth}, {\tt{16}})\index{every-member-sizep}\-
\end{tabbing}


\noindent{\sc Event}:   Disable every-member-sizep-update-nth.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-4-to-7 \\ \index{state-4-to-7}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar4\/}} $=$ {\rm{nat-to-bv}}\,({\tt{4}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar4\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{fetch-oprd-a-oracle}}\,({\it{i-reg\/}}, {\it{n\/}})\index{fetch-oprd-a-oracle})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{7}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file}, \\ 
{\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
\=\+{\bf if }{\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a} \\ 
{\bf then }{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-reg-file})\-\index{v-nth} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
\=\+{\bf if }{\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a} \\ 
{\bf then }{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+$\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-direct-reg-a}}\,({\it{i-reg\/}})\index{b-direct-reg-a}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-a-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-a-addr-out})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-4-to-7.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Fetch operand B, doing pre-decrement if necessary                   ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;



\end{verbatim}\begin{tabbing}{\sc Definition}:\index{fetch-oprd-b-reg-file} \\  
\=\+{\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-b-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-dec}, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-dec}}\,({\rm{v-nth}}\,({\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, {\it{reg-file\/}})\index{v-nth})\index{v-nat-dec})\-\index{update-v-nth}\-
\end{tabbing}

\begin{verbatim}; Both of the following lemmas are needed, as RAMP is enabled sometimes

\end{verbatim}\begin{tabbing}{\sc Theorem}:  ramp-fetch-oprd-b-reg-file \\ \index{ramp-fetch-oprd-b-reg-file}
\=\+(({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) $\wedge$ {\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp}) \\ 
$\rightarrow$$\;\;\;\;$(\=\+({\rm{length}}\,({\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file})\index{length} $=$ {\tt{8}}) \\ 
$\wedge$$\;\;\;\;${\rm{every-member-sizep}}\,({\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file}, {\it{m\/}})\index{every-member-sizep})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-fetch-oprd-b-reg-file-2 \\ \index{ramp-fetch-oprd-b-reg-file-2}
\=\+(({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) $\wedge$ {\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp}) \\ 
$\rightarrow$$\;\;\;\;${\rm{ramp}}\,({\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file}, {\it{m\/}}, {\tt{8}})\index{ramp}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{fetch-oprd-b-addr-out} \\  
\=\+{\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-indirect-reg-b-dec}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-dec} \\ 
{\bf then }{\rm{v-nat-dec}}\,({\rm{v-nth}}\,({\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, {\it{reg-file\/}})\index{v-nth})\index{v-nat-dec} \\ 
{\bf else }{\rm{v-nth}}\,({\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, {\it{reg-file\/}})\index{v-nth}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  sizep-fetch-oprd-b-addr-out \\ \index{sizep-fetch-oprd-b-addr-out}
\=\+(({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) $\wedge$ {\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp}) \\ 
$\rightarrow$$\;\;\;\;$({\rm{size}}\,({\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out})\index{size} $=$ {\it{m\/}})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-7-to-8 \\ \index{state-7-to-8}
\=\+({\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} $\wedge$ ({\it{mar7\/}} $=$ {\rm{nat-to-bv}}\,({\tt{7}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar7\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file}, \\ 
{\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-7-to-8.

\addvspace{18pt}

\begin{verbatim}; The next two lemmas are never used as rewrite rules.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-8-to-9-reg \\ \index{state-8-to-9-reg}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar8\/}} $=$ {\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar8\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dt-any\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{9}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-9-to-10-reg \\ \index{state-9-to-10-reg}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar9\/}} $=$ {\rm{nat-to-bv}}\,({\tt{9}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar9\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\rm{v-nth}}\,({\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, {\it{reg-file\/}})\index{v-nth}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\begin{tabbing}{\sc Theorem}:  state-8-to-9-mem-init \\ \index{state-8-to-9-mem-init}
\=\+(({\it{mar8\/}} $=$ {\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) $\wedge$ ($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar8\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-8-to-9-mem-init.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-8-to-9-mem-help \\ \index{state-8-to-9-mem-help}
\=\+(({\it{mar8\/}} $=$ {\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) $\wedge$ ($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar8\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{cons}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\it{oracle\/}}))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{big-machine}}\,(\=\+{\it{mar8\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\it{oracle\/}})\-\index{big-machine})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-8-to-9-mem-help.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-8-to-9-mem-wait \\ \index{state-8-to-9-mem-wait}
\=\+(({\it{mar8\/}} $=$ {\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) $\wedge$ ($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar8\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-8-to-9-mem-wait.

\addvspace{18pt}


\begin{verbatim}; the next two are never used as rewrites.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-8-to-9-mem-dtack \\ \index{state-8-to-9-mem-dtack}
\=\+(\=\+({\it{mar8\/}} $=$ {\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar8\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{9}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\begin{tabbing}{\sc Theorem}:  state-9-to-10-mem \\ \index{state-9-to-10-mem}
\=\+(\=\+({\it{mar9\/}} $=$ {\rm{nat-to-bv}}\,({\tt{9}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{visual-mem\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar9\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}

\begin{verbatim}; We now piece together states 7, 8, 9, and 10 for the reg case:

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-7-to-8-to-9-to-10-reg \\ \index{state-7-to-8-to-9-to-10-reg}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar7\/}} $=$ {\rm{nat-to-bv}}\,({\tt{7}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar7\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file}, \\ 
{\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file})\-\index{v-nth}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-7-to-8-to-9-to-10-reg.

\addvspace{18pt}


\begin{verbatim}; and now we do the same thing for 8, 9 and 10 in the mem case.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-8-to-9-to-10-mem-dtack \\ \index{state-8-to-9-to-10-mem-dtack}
\=\+(\=\+({\it{mar8\/}} $=$ {\rm{nat-to-bv}}\,({\tt{8}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar8\/}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\rm{trunc}}\,({\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\rm{v-nth}}\,({\it{addr-out\/}}, {\it{real-mem\/}})\index{v-nth}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{t}}, {\bf{f}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-5-to-6-to-7-mem-dtack.

\addvspace{18pt}


\begin{verbatim}; Finally, we do the entire transition from state 7 to state 10.  We first
; define the oracle necessary to drive the machine through the sequence.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{fetch-oprd-b-oracle} \\  
\=\+{\rm{fetch-oprd-b-oracle}}\,({\it{i-reg\/}}, {\it{n\/}})\index{fetch-oprd-b-oracle} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}$\;\;${\bf then }{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})) \\ 
{\bf else }{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-)\-)\-$\;${\bf  endif}\-\-
\end{tabbing}


\begin{tabbing}{\sc Theorem}:  state-7-to-10 \\ \index{state-7-to-10}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar7\/}} $=$ {\rm{nat-to-bv}}\,({\tt{7}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar7\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{fetch-oprd-b-oracle}}\,({\it{i-reg\/}}, {\it{n\/}})\index{fetch-oprd-b-oracle})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file}, \\ 
{\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
\=\+{\bf if }{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b} \\ 
{\bf then }{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\rm{fetch-oprd-b-reg-file}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-reg-file})\-\index{v-nth} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-, \\ 
{\it{i-reg\/}}, \\ 
\=\+{\bf if }{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b} \\ 
{\bf then }{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+$\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}, \\ 
{\it{data-out\/}}, \\ 
{\rm{fetch-oprd-b-addr-out}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{fetch-oprd-b-addr-out})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-7-to-10.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                   ALU, results to memory or register                         ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{alu-c-flag} \\  
\=\+{\rm{alu-c-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}})\index{alu-c-flag} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set} \\ 
{\bf then }{\rm{c}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{c} \\ 
{\bf else }{\it{c-flag\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{alu-v-flag} \\  
\=\+{\rm{alu-v-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}})\index{alu-v-flag} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set} \\ 
{\bf then }{\rm{v}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{v} \\ 
{\bf else }{\it{v-flag\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{alu-z-flag} \\  
\=\+{\rm{alu-z-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{z-flag\/}})\index{alu-z-flag} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set} \\ 
{\bf then }{\rm{b-bv-zerop}}\,({\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv})\index{b-bv-zerop} \\ 
{\bf else }{\it{z-flag\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{alu-n-flag} \\  
\=\+{\rm{alu-n-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{n-flag\/}})\index{alu-n-flag} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-cc-set}}\,({\it{i-reg\/}})\index{b-cc-set} \\ 
{\bf then }{\rm{bitn}}\,(\=\+{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{bitn} \\ 
{\bf else }{\it{n-flag\/}}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  boolp-alu-c-flag \\ \index{boolp-alu-c-flag}
{\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} $\rightarrow$ {\rm{boolp}}\,({\rm{alu-c-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}})\index{alu-c-flag})\index{boolp}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  boolp-alu-v-flag \\ \index{boolp-alu-v-flag}
{\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} $\rightarrow$ {\rm{boolp}}\,({\rm{alu-v-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}})\index{alu-v-flag})\index{boolp}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  boolp-alu-z-flag \\ \index{boolp-alu-z-flag}
{\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} $\rightarrow$ {\rm{boolp}}\,({\rm{alu-z-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{z-flag\/}})\index{alu-z-flag})\index{boolp}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  boolp-alu-n-flag \\ \index{boolp-alu-n-flag}
{\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} $\rightarrow$ {\rm{boolp}}\,({\rm{alu-n-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{n-flag\/}})\index{alu-n-flag})\index{boolp}
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-10-to-11 \\ \index{state-10-to-11}
\=\+(\=\+({\it{mar10\/}} $=$ {\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{no-store\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar10\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{alu-c-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}})\index{alu-c-flag}, \\ 
{\rm{alu-v-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}})\index{alu-v-flag}, \\ 
{\rm{alu-z-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{z-flag\/}})\index{alu-z-flag}, \\ 
{\rm{alu-n-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{n-flag\/}})\index{alu-n-flag}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-10-to-11.

\addvspace{18pt}

\noindent{\sc Event}:   Disable alu-c-flag.

\addvspace{18pt}

\noindent{\sc Event}:   Disable alu-v-flag.

\addvspace{18pt}

\noindent{\sc Event}:   Disable alu-z-flag.

\addvspace{18pt}

\noindent{\sc Event}:   Disable alu-n-flag.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  state-11-to-12-reg \\ \index{state-11-to-12-reg}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$({\it{mar11\/}} $=$ {\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar11\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-v-nth}}\,(\=\+$\neg$ {\it{no-store\/}}, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\it{reg-file\/}}, \\ 
{\it{data-out\/}})\-\index{update-v-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-11-to-12-mem-no-store \\ \index{state-11-to-12-mem-no-store}
\=\+(\=\+({\it{mar11\/}} $=$ {\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;$({\it{no-store\/}} $=$ {\bf{t}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar11\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\begin{tabbing}{\sc Theorem}:  state-11-to-12-mem-init-store \\ \index{state-11-to-12-mem-init-store}
\=\+(\=\+({\it{mar11\/}} $=$ {\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;$({\it{no-store\/}} $=$ {\bf{f}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar11\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-11-to-12-mem-init-store.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-11-to-12-mem-help \\ \index{state-11-to-12-mem-help}
\=\+(\=\+({\it{mar11\/}} $=$ {\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;$({\it{no-store\/}} $=$ {\bf{f}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar11\/}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{cons}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\it{oracle\/}}))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{big-machine}}\,(\=\+{\it{mar11\/}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\sc{machine-size}}\index{machine-size})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{t}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\it{oracle\/}})\-\index{big-machine})\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-11-to-12-mem-help.

\addvspace{18pt}

\begin{tabbing}{\sc Definition}:\index{state-11-to-11-induction} \\  
\=\+{\rm{state-11-to-11-induction}}\,(\=\+{\it{dtack\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\it{n\/}})\-\index{state-11-to-11-induction} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{n\/}} $\simeq {\tt{0}}$$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\rm{state-11-to-11-induction}}\,(\=\+{\bf{f}}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{trunc}}\,(\=\+{\sc{default-visual-mem-value}}\index{default-visual-mem-value}, \\ 
{\sc{machine-size}}\index{machine-size})\-\index{trunc}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{t}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\it{n\/}} $-\;1$)\-\index{state-11-to-11-induction}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-11-to-12-mem-wait-store \\ \index{state-11-to-12-mem-wait-store}
\=\+(\=\+({\it{mar11\/}} $=$ {\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;$({\it{no-store\/}} $=$ {\bf{f}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar11\/}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{t}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-11-to-12-mem-wait-store.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  state-11-to-12-mem-dtack-store \\ \index{state-11-to-12-mem-dtack-store}
\=\+(\=\+{\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$({\it{mar11\/}} $=$ {\rm{nat-to-bv}}\,({\tt{11}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;$({\it{no-store\/}} $=$ {\bf{f}}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar11\/}}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{t}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\rm{update-v-nth}}\,({\bf{t}}, {\it{addr-out\/}}, {\it{real-mem\/}}, {\it{data-out\/}})\index{update-v-nth}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{t}}, {\bf{t}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-11-to-12-mem-dtack-store.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  state-10-to-12-reg \\ \index{state-10-to-12-reg}
\=\+(\=\+({\it{mar10\/}} $=$ {\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{no-store\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{a-reg\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar10\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\rm{update-v-nth}}\,(\=\+{\rm{b-store-alu-result}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{i-reg\/}})\-\index{b-store-alu-result}, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv})\-\index{update-v-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{alu-c-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}})\index{alu-c-flag}, \\ 
{\rm{alu-v-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}})\index{alu-v-flag}, \\ 
{\rm{alu-z-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{z-flag\/}})\index{alu-z-flag}, \\ 
{\rm{alu-n-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{n-flag\/}})\index{alu-n-flag}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\it{addr-out\/}})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-10-to-12-reg.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  state-10-to-12-mem-no-store \\ \index{state-10-to-12-mem-no-store}
\=\+(\=\+({\it{mar10\/}} $=$ {\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{a-reg\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}) \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar10\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{alu-c-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}})\index{alu-c-flag}, \\ 
{\rm{alu-v-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}})\index{alu-v-flag}, \\ 
{\rm{alu-z-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{z-flag\/}})\index{alu-z-flag}, \\ 
{\rm{alu-n-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{n-flag\/}})\index{alu-n-flag}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\it{addr-out\/}})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-10-to-12-mem-no-store.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  state-10-to-12-mem-store \\ \index{state-10-to-12-mem-store}
\=\+(\=\+({\it{mar10\/}} $=$ {\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{no-store\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{a-reg\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}) \\ 
$\wedge$$\;\;\;\;${\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar10\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-)\-)\-)\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{t}}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{alu-c-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}})\index{alu-c-flag}, \\ 
{\rm{alu-v-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}})\index{alu-v-flag}, \\ 
{\rm{alu-z-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{z-flag\/}})\index{alu-z-flag}, \\ 
{\rm{alu-n-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{n-flag\/}})\index{alu-n-flag}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\rm{update-v-nth}}\,(\=\+{\bf{t}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv})\-\index{update-v-nth}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\bf{t}}, \\ 
{\bf{t}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\it{addr-out\/}})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-10-to-12-mem-store.

\addvspace{18pt}  

\begin{tabbing}{\sc Definition}:\index{alu-oracle} \\  
\=\+{\rm{alu-oracle}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{n\/}})\index{alu-oracle} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}$\;\;${\bf then }{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})) \\ 
{\bf elseif }{\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result} \\ 
{\bf then }{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})), \\ 
{\rm{append}}\,(\=\+{\rm{list-of-n-plus-1-dtack-reset-off}}\,({\it{n\/}})\index{list-of-n-plus-1-dtack-reset-of!f}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{t}}, {\bf{f}}), {\rm{list}}\,({\bf{t}}, {\bf{f}})))\-)\-)\- \\ 
{\bf else }{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}}))$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  update-nth-f \\ \index{update-nth-f}
{\rm{update-nth}}\,({\bf{f}}, {\it{n\/}}, {\it{lst\/}}, {\it{val\/}})\index{update-nth} $=$ {\it{lst\/}}
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{mem-store-flag} \\  
\=\+{\rm{mem-store-flag}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}})\index{mem-store-flag} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}$\;\;${\bf then }{\bf{f}} \\ 
{\bf else }{\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-10-to-12 \\ \index{state-10-to-12}
\=\+(\=\+{\rm{boolp}}\,({\it{no-store\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{a-reg\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar10\/}} $=$ {\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar10\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{alu-oracle}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{n\/}})\index{alu-oracle})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\rm{mem-store-flag}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}})\index{mem-store-flag}, \\ 
{\rm{mem-store-flag}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}})\index{mem-store-flag}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\rm{update-v-nth}}\,(\=\+\=\+{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b} \\ 
$\wedge$$\;\;\;\;${\rm{b-store-alu-result}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{i-reg\/}})\-\index{b-store-alu-result}\-, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv})\-\index{update-v-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{alu-c-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}})\index{alu-c-flag}, \\ 
{\rm{alu-v-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}})\index{alu-v-flag}, \\ 
{\rm{alu-z-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{z-flag\/}})\index{alu-z-flag}, \\ 
{\rm{alu-n-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{n-flag\/}})\index{alu-n-flag}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\rm{update-v-nth}}\,(\=\+\=\+($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}) \\ 
$\wedge$$\;\;\;\;${\rm{b-store-alu-result}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{i-reg\/}})\-\index{b-store-alu-result}\-, \\ 
{\it{addr-out\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv})\-\index{update-v-nth}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\rm{mem-store-flag}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{mem-store-flag}, \\ 
{\rm{mem-store-flag}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{mem-store-flag}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\it{addr-out\/}})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-10-to-12.

\addvspace{18pt}


\noindent{\sc Event}:   Disable mem-store-flag.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                  Post-increment operations                                   ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  state-12-to-13 \\ \index{state-12-to-13}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\rm{truep}}\,({\it{mem-store-flag\/}}) $\vee$ {\rm{falsep}}\,({\it{mem-store-flag\/}})) \\ 
$\wedge$$\;\;\;\;$({\it{mar12\/}} $=$ {\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar12\/}}, \\ 
{\bf{f}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}})\-\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\it{mem-store-flag\/}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{13}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-a-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-inc}, \\ 
{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,({\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, {\it{reg-file\/}})\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\begin{tabbing}{\sc Theorem}:  state-13-to-1 \\ \index{state-13-to-1}
\=\+({\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} $\wedge$ ({\it{mar13\/}} $=$ {\rm{nat-to-bv}}\,({\tt{13}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv})) \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar13\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{list}}\,({\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-b-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-inc}, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,({\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, {\it{reg-file\/}})\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{reg-file-post-inc} \\  
\=\+{\rm{reg-file-post-inc}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{reg-file-post-inc} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-b-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-inc}, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-a-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-inc}, \\ 
{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,({\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, {\it{reg-file\/}})\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-a-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-inc}, \\ 
{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\it{reg-file\/}})\-\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth})\-\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-12-to-1 \\ \index{state-12-to-1}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\rm{truep}}\,({\it{mem-store-flag\/}}) $\vee$ {\rm{falsep}}\,({\it{mem-store-flag\/}})) \\ 
$\wedge$$\;\;\;\;$({\it{mar12\/}} $=$ {\rm{nat-to-bv}}\,({\tt{12}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar12\/}}, \\ 
{\bf{f}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\it{mem-store-flag\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{addr-out\/}})\-\index{watch-dog}, \\ 
{\rm{list}}\,({\rm{list}}\,({\it{mem-store-flag\/}}, {\bf{f}}), {\rm{list}}\,({\bf{f}}, {\bf{f}})))\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{reg-file-post-inc}}\,({\it{i-reg\/}}, {\it{reg-file\/}})\index{reg-file-post-inc}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,({\bf{f}}, {\bf{f}}, {\bf{f}}, {\it{data-out\/}}, {\it{addr-out\/}})\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-12-to-1.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;                  Pasting together the steps                                  ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


; In state-4-to-7 we rewrite to something of the form (list ... (if a b c) ...).
; When applying big-machine-append the variable M is bound to the rewritten version
; of this form.  But the rewriter moves the if's out, producing 
; (if a (list ... b ...) (list ... c ...)).  We then, in simplifying the rhs of
; big-machine-append, rewrite (cadr M) to get the new read.  We want it to rewrite to
; f but in fact it rewrites to (cadr (if a (list mar7 f ...) (list mar7 f ...))).
; Then, state-7-to-10 doesn't unify.  So we prove the following two facts.
; Because of these, we don't really care whether our state steppers return
; lists with if's inside or outside.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  car-if \\ \index{car-if}
\=\+{\rm{car}}\,(\=\+{\bf if }{\it{a\/}}$\;\;${\bf then }{\it{b\/}} \\ 
{\bf else }{\it{c\/}}$\;${\bf  endif}\-) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{a\/}}$\;\;${\bf then }{\rm{car}}\,({\it{b\/}}) \\ 
{\bf else }{\rm{car}}\,({\it{c\/}})$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  cdr-if \\ \index{cdr-if}
\=\+{\rm{cdr}}\,(\=\+{\bf if }{\it{a\/}}$\;\;${\bf then }{\it{b\/}} \\ 
{\bf else }{\it{c\/}}$\;${\bf  endif}\-) \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{a\/}}$\;\;${\bf then }{\rm{cdr}}\,({\it{b\/}}) \\ 
{\bf else }{\rm{cdr}}\,({\it{c\/}})$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{reg-file-after-a-b} \\  
\=\+{\rm{reg-file-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-a-b} \\ 
$=$$\;\;\;\;${\rm{fetch-oprd-b-reg-file}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth})\index{v-nat-inc})\-\index{update-nth})\-\index{fetch-oprd-a-reg-file})\-\index{fetch-oprd-b-reg-file}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{addr-out-after-a-b} \\  
\=\+{\rm{addr-out-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{addr-out-after-a-b} \\ 
$=$$\;\;\;\;${\rm{fetch-oprd-b-addr-out}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth})\index{v-nat-inc})\-\index{update-nth})\-\index{fetch-oprd-a-reg-file})\-\index{fetch-oprd-b-addr-out}\-
\end{tabbing}


\begin{tabbing}{\sc Definition}:\index{a-reg-after-a-b} \\  
\=\+{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-a}}\,({\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth})\index{b-direct-reg-a} \\ 
{\bf then }{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth})\index{bv-oprd-a}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{v-nat-inc})\-\index{update-nth})\-\index{fetch-oprd-a-reg-file})\-\index{v-nth} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{fetch-oprd-a-addr-out}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth})\index{v-nat-inc})\-\index{update-nth})\-\index{fetch-oprd-a-addr-out}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{b-reg-after-a-b} \\  
\=\+{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-b}}\,({\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth})\index{b-direct-reg-b} \\ 
{\bf then }{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth})\index{bv-oprd-b}, \\ 
{\rm{fetch-oprd-b-reg-file}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth})\index{v-nat-inc})\-\index{update-nth})\-\index{fetch-oprd-a-reg-file})\-\index{fetch-oprd-b-reg-file})\-\index{v-nth} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{fetch-oprd-b-addr-out}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth})\index{v-nat-inc})\-\index{update-nth})\-\index{fetch-oprd-a-reg-file})\-\index{fetch-oprd-b-addr-out}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{visual-mem-after-a-b} \\  
\=\+{\rm{visual-mem-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{visual-mem-after-a-b} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-b}}\,({\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth})\index{b-direct-reg-b} \\ 
{\bf then }{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{fetch-oprd-b-addr-out}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{fetch-oprd-a-reg-file}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{v-nat-inc}}\,({\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth})\index{v-nat-inc})\-\index{update-nth})\-\index{fetch-oprd-a-reg-file})\-\index{fetch-oprd-b-addr-out}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{dtack-after-a-b} \\  
\=\+{\rm{dtack-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{dtack-after-a-b} \\ 
$=$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth})\index{b-direct-reg-b})\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{a-b-oracle} \\  
\=\+{\rm{a-b-oracle}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{i\/}}, {\it{n\/}}, {\it{m\/}})\index{a-b-oracle} \\ 
$=$$\;\;\;\;${\rm{append}}\,(\=\+{\rm{fetch-ir-oracle}}\,({\it{i\/}})\index{fetch-ir-oracle}, \\ 
{\rm{append}}\,(\=\+{\rm{fetch-oprd-a-oracle}}\,({\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, {\it{n\/}})\index{fetch-oprd-a-oracle}, \\ 
{\rm{fetch-oprd-b-oracle}}\,({\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, {\it{m\/}})\index{fetch-oprd-b-oracle})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-1-to-10 \\ \index{state-1-to-10}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar1\/}} $=$ {\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar1\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{a-b-oracle}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{i\/}}, {\it{n\/}}, {\it{m\/}})\index{a-b-oracle})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\rm{dtack-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{dtack-after-a-b}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\rm{reg-file-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-a-b}, \\ 
{\rm{addr-out-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{addr-out-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{visual-mem-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{visual-mem-after-a-b}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{watch-dog}}\,(\=\+{\rm{dtack-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{dtack-after-a-b}, \\ 
{\bf{f}}, \\ 
{\rm{dtack-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{dtack-after-a-b}, \\ 
{\it{data-out\/}}, \\ 
{\rm{addr-out-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{addr-out-after-a-b})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\begin{tabbing}{\sc Definition}:\index{reg-file-alu} \\  
\=\+{\rm{reg-file-alu}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{reg-file\/}}, {\it{a-reg\/}}, {\it{b-reg\/}})\index{reg-file-alu} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+\=\+{\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b} \\ 
$\wedge$$\;\;\;\;${\rm{b-store-alu-result}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{i-reg\/}})\-\index{b-store-alu-result}\-, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv})\-\index{update-v-nth}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{reg-file-from-alu-thru-post-inc} \\  
\=\+{\rm{reg-file-from-alu-thru-post-inc}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}})\-\index{reg-file-from-alu-thru-post-inc} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-b-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-b-inc}, \\ 
{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-a-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-inc}, \\ 
{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\rm{reg-file-alu}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}})\-\index{reg-file-alu}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\rm{reg-file-alu}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}})\-\index{reg-file-alu})\-\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\it{i-reg\/}})\index{bv-oprd-b}, \\ 
{\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-a-inc}}\,({\it{i-reg\/}})\index{b-indirect-reg-a-inc}, \\ 
{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\rm{reg-file-alu}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}})\-\index{reg-file-alu}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\it{i-reg\/}})\index{bv-oprd-a}, \\ 
{\rm{reg-file-alu}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}})\-\index{reg-file-alu})\-\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth})\-\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{real-mem-thru-post-inc} \\  
\=\+{\rm{real-mem-thru-post-inc}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}})\-\index{real-mem-thru-post-inc} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+\=\+($\neg$ {\rm{b-direct-reg-b}}\,({\it{i-reg\/}})\index{b-direct-reg-b}) \\ 
$\wedge$$\;\;\;\;${\rm{b-store-alu-result}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{i-reg\/}})\-\index{b-store-alu-result}\-, \\ 
{\it{addr-out\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv})\-\index{update-v-nth}\-
\end{tabbing}

\begin{tabbing}{\sc Definition}:\index{alu-post-inc-oracle} \\  
\=\+{\rm{alu-post-inc-oracle}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{n\/}})\index{alu-post-inc-oracle} \\ 
$=$$\;\;\;\;${\rm{append}}\,(\=\+{\rm{alu-oracle}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{n\/}})\index{alu-oracle}, \\ 
{\rm{list}}\,(\=\+{\rm{list}}\,({\rm{mem-store-flag}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}})\index{mem-store-flag}, {\bf{f}}), \\ 
{\rm{list}}\,({\bf{f}}, {\bf{f}}))\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-if \\ \index{ramp-if}
\=\+{\rm{ramp}}\,(\=\+\=\+{\bf if }{\it{c\/}}$\;\;${\bf then }{\it{a\/}} \\ 
{\bf else }{\it{b\/}}$\;${\bf  endif}\-, \\ 
{\it{i\/}}, \\ 
{\it{j\/}})\-\index{ramp} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{c\/}}$\;\;${\bf then }{\rm{ramp}}\,({\it{a\/}}, {\it{i\/}}, {\it{j\/}})\index{ramp} \\ 
{\bf else }{\rm{ramp}}\,({\it{b\/}}, {\it{i\/}}, {\it{j\/}})\index{ramp}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-update-nth \\ \index{ramp-update-nth}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\it{width\/}}, {\it{number\/}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{value\/}}, {\it{width\/}})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{boolean\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;$({\it{number\/}} $\not<$ {\it{place\/}}))\- \\ 
$\rightarrow$$\;\;\;\;${\rm{ramp}}\,({\rm{update-nth}}\,({\it{boolean\/}}, {\it{place\/}}, {\it{reg-file\/}}, {\it{value\/}})\index{update-nth}, {\it{width\/}}, {\it{number\/}})\index{ramp}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-10-to-1 \\ \index{state-10-to-1}
\=\+(\=\+{\rm{boolp}}\,({\it{no-store\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{a-reg\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar10\/}} $=$ {\rm{nat-to-bv}}\,({\tt{10}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar10\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog-history\/}}, \\ 
{\rm{alu-post-inc-oracle}}\,({\it{i-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{n\/}})\index{alu-post-inc-oracle})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-store-alu-result}}\,({\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{i-reg\/}})\index{b-store-alu-result}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,({\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\index{bv-alu-cv})\index{bv}, \\ 
{\rm{reg-file-from-alu-thru-post-inc}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}})\-\index{reg-file-from-alu-thru-post-inc}, \\ 
{\it{addr-out\/}}, \\ 
{\rm{alu-c-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}})\index{alu-c-flag}, \\ 
{\rm{alu-v-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{v-flag\/}})\index{alu-v-flag}, \\ 
{\rm{alu-z-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{z-flag\/}})\index{alu-z-flag}, \\ 
{\rm{alu-n-flag}}\,({\it{i-reg\/}}, {\it{a-reg\/}}, {\it{b-reg\/}}, {\it{c-flag\/}}, {\it{n-flag\/}})\index{alu-n-flag}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\rm{real-mem-thru-post-inc}}\,(\=\+{\it{i-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}})\-\index{real-mem-thru-post-inc}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\it{i-reg\/}})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\it{addr-out\/}})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-10-to-1.

\addvspace{18pt}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;            The lemmas that follow culminate in lemma STATE-1-to-1            ;;
;;            which is a statement of what FM8501 does upon executing           ;;
;;            an instruction.  FM8501 executes one memory based instruction     ;;
;;            by starting in a state where the MAR is "1", executing some       ;;
;;            of micro-states eventually taking it back to a place where        ;;
;;            MAR is equal to "1".                                              ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  sizep-a-reg-after-a-b \\ \index{sizep-a-reg-after-a-b}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$({\rm{size}}\,({\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b})\index{size} $=$ {\sc{machine-size}}\index{machine-size})\-
\end{tabbing}


\begin{tabbing}{\sc Theorem}:  sizep-addr-out-after-a-b \\ \index{sizep-addr-out-after-a-b}
\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\rightarrow$$\;\;\;\;$({\rm{size}}\,({\rm{addr-out-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{addr-out-after-a-b})\index{size} $=$ {\sc{machine-size}}\index{machine-size})\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-reg-file-after-a-b \\ \index{ramp-reg-file-after-a-b}
\=\+(({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) $\wedge$ {\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp}) \\ 
$\rightarrow$$\;\;\;\;${\rm{ramp}}\,({\rm{reg-file-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-a-b}, {\it{m\/}}, {\tt{8}})\index{ramp}\-
\end{tabbing}



\begin{tabbing}{\sc Definition}:\index{state-1-to-1-oracle} \\  
\=\+{\rm{state-1-to-1-oracle}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{ir-wait\/}}, \\ 
{\it{a-wait\/}}, \\ 
{\it{b-wait\/}}, \\ 
{\it{store-wait\/}})\-\index{state-1-to-1-oracle} \\ 
$=$$\;\;\;\;${\rm{append}}\,(\=\+{\rm{a-b-oracle}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{ir-wait\/}}, {\it{a-wait\/}}, {\it{b-wait\/}})\index{a-b-oracle}, \\ 
{\rm{alu-post-inc-oracle}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{store-wait\/}})\-\index{alu-post-inc-oracle})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  state-1-to-1 \\ \index{state-1-to-1}
\=\+(\=\+{\rm{boolp}}\,({\it{no-store\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{data-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{sizep}}\,({\it{addr-out\/}}, {\sc{machine-size}}\index{machine-size})\index{sizep} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;$({\it{mar1\/}} $=$ {\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}))\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{big-machine}}\,(\=\+{\it{mar1\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{state-1-to-1-oracle}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{ir-wait\/}}, \\ 
{\it{a-wait\/}}, \\ 
{\it{b-wait\/}}, \\ 
{\it{store-wait\/}})\-\index{state-1-to-1-oracle})\-\index{big-machine} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
$\neg$ {\rm{b-store-alu-result}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth})\-\index{b-store-alu-result}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\rm{reg-file-from-alu-thru-post-inc}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{reg-file-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-a-b}, \\ 
{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b})\-\index{reg-file-from-alu-thru-post-inc}, \\ 
{\rm{addr-out-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{addr-out-after-a-b}, \\ 
{\rm{alu-c-flag}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}})\-\index{alu-c-flag}, \\ 
{\rm{alu-v-flag}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}})\-\index{alu-v-flag}, \\ 
{\rm{alu-z-flag}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\it{z-flag\/}})\-\index{alu-z-flag}, \\ 
{\rm{alu-n-flag}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{alu-n-flag}, \\ 
{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\rm{real-mem-thru-post-inc}}\,(\=\+{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{addr-out-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{addr-out-after-a-b}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b})\-\index{real-mem-thru-post-inc}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\rm{addr-out-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{addr-out-after-a-b})\-\index{watch-dog})\-)\-\-
\end{tabbing}


\noindent{\sc Event}:   Disable state-1-to-1.

\addvspace{18pt}


\begin{tabbing}{\sc Theorem}:  nth-update-nth \\ \index{nth-update-nth}
\=\+{\rm{nth}}\,({\it{i\/}}, {\rm{update-nth}}\,({\it{c\/}}, {\it{j\/}}, {\it{lst\/}}, {\it{x\/}})\index{update-nth})\index{nth} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{truep}}\,({\it{c\/}}) $\wedge$ ({\rm{fix}}\,({\it{i\/}}) $=$ {\rm{fix}}\,({\it{j\/}})) $\wedge$ ({\it{j\/}} $<$ {\rm{length}}\,({\it{lst\/}})\index{length})$\;\;${\bf then }{\it{x\/}} \\ 
{\bf else }{\rm{nth}}\,({\it{i\/}}, {\it{lst\/}})\index{nth}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Software specification of FM8501.                                   ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Helping definitions for the specification of the software           ;;
;;          machine.  Function SOFT is the actual definition defining           ;;
;;          the operation of the FM8501.                                        ;;
;;                                                                              ;;
;;          When programming the FM8501 the user see eight general purpose      ;;
;;          registers (register file), four flag bits (carry, overflow,         ;;
;;          negative, and zero), and the memory.  Instruction execution         ;;
;;          is accomplished by reading the memory value pointed to by the       ;;
;;          program counter (register 0), and interpreting this memory word     ;;
;;          as an instruction to be executed.  The execution of an instruction  ;;
;;          may modify all visable registers.  The flag registers may be        ;;
;;          updated only once per instruction.  The memory may be updated       ;;
;;          only once per instruction.  The register file may be updated a      ;;
;;          maximum of four times in six opportunities.  The first update to    ;;
;;          the register file, which always occurs, is the incrementing of      ;;
;;          the program counter.  Next comes the possible pre-decrement         ;;
;;          operation of both operands.  The result of the ALU may be next      ;;
;;          stored into the register file.  Lastly, there may be two            ;;
;;          post-increment operations.  An operand cannot be both               ;;
;;          pre-decremented and post-incremented.                               ;;
;;                                                                              ;;
;;          The functions below generate the next state for the memory and      ;;
;;          the register file given an instruction.  These are grouped          ;;
;;          together into an interpreter called SOFT.  SOFT executed one        ;;
;;          instruction per recursive call.                                     ;;
;;                                                                              ;;
;;          The next state for the register file (REG-FILE) is created by       ;;
;;          the composition of several functions.  Each function describes      ;;
;;          the state of the register file at some point through the execution  ;;
;;          of an instruction.  Below are described the operation of the        ;;
;;          functions that update the register file.  All of these functions    ;;
;;          return a complete register file, which they may or may not of       ;;
;;          updated.                                                            ;;
;;                                                                              ;;
;;          reg-file-after-pc-increment --                                      ;;
;;               increments the PC (register 0)                                 ;;
;;                                                                              ;;
;;          reg-file-after-oprd-a-pre-decrement --                              ;;
;;               performs a pre-decrement operation for operand A if required,  ;;
;;               and included is the reg-file-after-pc-increment operation      ;;
;;                                                                              ;;
;;          reg-file-after-oprd-b-pre-decrement --                              ;;
;;               performs a pre-decrement operation for operand B if required,  ;;
;;               and included is the reg-file-after-oprd-a-pre-decrement        ;;
;;               operation                                                      ;;
;;                                                                              ;;
;;          reg-file-after-alu-write --                                         ;;
;;               writes the output of the ALU to the reg-file if required,      ;;
;;               and included is the reg-file-after-oprd-b-pre-decrement        ;;
;;               operation                                                      ;;
;;                                                                              ;;
;;          reg-file-after-oprd-a-post-increment --                             ;;
;;               performs a post-increment operation for operand A if required, ;;
;;               and included is the reg-file-after-alu-write operation         ;;
;;                                                                              ;;
;;          reg-file-after-oprd-b-post-increment --                             ;;
;;               performs a post-increment operation for operand B if required, ;;
;;               and included is the reg-file-after-oprd-a-post-increment       ;;
;;               operation                                                      ;;
;;                                                                              ;;
;;          The ALU requires three operands so its result can be calculated.    ;;
;;          The C-FLAG is readily available, but the A and B value for the      ;;
;;          ALU must be generated under instruction control.  The A value is    ;;
;;          fetched either from the register file or the memory, but not until  ;;
;;          both the PC has been incremented and the operand A pre-decrement    ;;
;;          performed.  The function A-VALUE-FOR-ALU-AFTER-OPRD-A-PRE-DECREMENT ;;
;;          generates the appropriate value.  The B value for the ALU is        ;;
;;          fetched from either the register file or memory, but not until the  ;;
;;          PC has been incremented and the possible operand A pre-decrement    ;;
;;          and operand B pre-decrement operations performed.  The function     ;;
;;          B-VALUE-FOR-ALU-AFTER-OPRD-B-PRE-DECREMENT generates the correct    ;;
;;          operand B value.                                                    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


;  This function increments the Program Counter (PC) by one.  The PC is
;  stored in register 0 in the register file.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{reg-file-after-pc-increment} \\  
\=\+{\rm{reg-file-after-pc-increment}}\,({\it{reg-file\/}})\index{reg-file-after-pc-increment} \\ 
$=$$\;\;\;\;${\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{v-nat-inc}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{v-nat-inc})\index{update-nth}\-
\end{tabbing}


\begin{verbatim};  This function extracts the current instruction from memory.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{current-instruction} \\  
{\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction} $=$ {\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}
\end{tabbing}


\begin{verbatim};  The result of this function are the contents of the register file after
;  the possible pre-decrement for operand A and the increment of PC.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{reg-file-after-oprd-a-pre-decre!ment} \\  
\=\+{\rm{reg-file-after-oprd-a-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-a-pre-decre!ment} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-a-dec}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-indirect-reg-a-dec}, \\ 
{\rm{bv-oprd-a}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-a}, \\ 
{\rm{reg-file-after-pc-increment}}\,({\it{reg-file\/}})\index{reg-file-after-pc-increment}, \\ 
{\rm{v-nat-dec}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-a}, \\ 
{\rm{reg-file-after-pc-increment}}\,({\it{reg-file\/}})\index{reg-file-after-pc-increment})\-\index{v-nth})\index{v-nat-dec})\-\index{update-v-nth}\-
\end{tabbing}


\begin{verbatim};  The result of this function are the contents of the register file after
;  the possible pre-decrement for operand B, the possible pre-decrement for
;  operand A and the increment of PC.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{reg-file-after-oprd-b-pre-decre!ment} \\  
\=\+{\rm{reg-file-after-oprd-b-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-b-pre-decre!ment} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-b-dec}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-indirect-reg-b-dec}, \\ 
{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-a-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-a-pre-decre!ment}, \\ 
{\rm{v-nat-dec}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-oprd-a-pre-decre!ment})\-\index{v-nth})\index{v-nat-dec})\-\index{update-v-nth}\-
\end{tabbing}


\begin{verbatim};  This function returns operand A for use in the ALU after the PC has been
;  incremented and the possible operand A pre-decrement has occured.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{a-value-for-alu-after-oprd-a-pre!-decrement} \\  
\=\+{\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-value-for-alu-after-oprd-a-pre!-decrement} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-a}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{b-direct-reg-a} \\ 
{\bf then }{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-a}, \\ 
{\rm{reg-file-after-pc-increment}}\,({\it{reg-file\/}})\index{reg-file-after-pc-increment})\-\index{v-nth} \\ 
{\bf elseif }{\rm{b-indirect-reg-a-dec}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{b-indirect-reg-a-dec} \\ 
{\bf then }{\rm{v-nth}}\,(\=\+{\rm{v-nat-dec}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-a}, \\ 
{\rm{reg-file-after-pc-increment}}\,({\it{reg-file\/}})\index{reg-file-after-pc-increment})\-\index{v-nth})\index{v-nat-dec}, \\ 
{\it{real-mem\/}})\-\index{v-nth} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-a}, \\ 
{\rm{reg-file-after-pc-increment}}\,({\it{reg-file\/}})\index{reg-file-after-pc-increment})\-\index{v-nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-\-
\end{tabbing}


\begin{verbatim};  This function returns operand B for use in the ALU after the PC has been
;  incremented, the possible operand A pre-decrement has occured, and the
;  possible operand B pre-decrement has occured.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{b-value-for-alu-after-oprd-b-pre!-decrement} \\  
\=\+{\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-value-for-alu-after-oprd-b-pre!-decrement} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\rm{b-direct-reg-b}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{b-direct-reg-b} \\ 
{\bf then }{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-a-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-a-pre-decre!ment})\-\index{v-nth} \\ 
{\bf elseif }{\rm{b-indirect-reg-b-dec}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{b-indirect-reg-b-dec} \\ 
{\bf then }{\rm{v-nth}}\,(\=\+{\rm{v-nat-dec}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-oprd-a-pre-decre!ment})\-\index{v-nth})\index{v-nat-dec}, \\ 
{\it{real-mem\/}})\-\index{v-nth} \\ 
{\bf else }{\rm{v-nth}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-oprd-a-pre-decre!ment})\-\index{v-nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};  This function returns the result of the ALU on operand A, operand B, and
;  the carry flag.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{bv-alu-cv-results} \\  
\=\+{\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results} \\ 
$=$$\;\;\;\;${\rm{bv-alu-cv}}\,(\=\+{\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-value-for-alu-after-oprd-a-pre!-decrement}, \\ 
{\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-value-for-alu-after-oprd-b-pre!-decrement}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-alu-op-code})\-\index{bv-alu-cv}\-
\end{tabbing}

\begin{verbatim};  This function returns the result of a possible storing of the ALU result
;  into the register file.  Note that this function takes into account the
;  possible changes that may have been inflicted on the register file by some
;  pre-decrement operations and the PC increment.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{reg-file-after-alu-write} \\  
\=\+{\rm{reg-file-after-alu-write}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}})\index{reg-file-after-alu-write} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+\=\+{\rm{b-store-alu-result-with-ifs}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\-\index{b-store-alu-result-with-ifs} \\ 
$\wedge$$\;\;\;\;${\rm{b-direct-reg-b}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-direct-reg-b}\-, \\ 
{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-b-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-b-pre-decre!ment}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\-\index{update-v-nth}\-
\end{tabbing}

\begin{verbatim};  This function returns the result of a possible storing of the ALU result
;  into the memory.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{real-mem-after-alu-write} \\  
\=\+{\rm{real-mem-after-alu-write}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}})\index{real-mem-after-alu-write} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+\=\+{\rm{b-store-alu-result-with-ifs}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\-\index{b-store-alu-result-with-ifs} \\ 
$\wedge$$\;\;\;\;$($\neg$ {\rm{b-direct-reg-b}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-direct-reg-b})\-, \\ 
{\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-oprd-b-pre-decre!ment})\-\index{v-nth}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\-\index{update-v-nth}\-
\end{tabbing}


\begin{verbatim};  This function returns the result of a possible post-increment of operand A
;  after the possible storing of the ALU result, the pre-decrements of A and B,
;  and the PC increment.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{reg-file-after-oprd-a-post-incre!ment} \\  
\=\+{\rm{reg-file-after-oprd-a-post-increment}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-oprd-a-post-incre!ment} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-a-inc}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-indirect-reg-a-inc}, \\ 
{\rm{bv-oprd-a}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-a}, \\ 
{\rm{reg-file-after-alu-write}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-alu-write}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-a}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-a}, \\ 
{\rm{reg-file-after-alu-write}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-alu-write})\-\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth}\-
\end{tabbing}


\begin{verbatim};  This function returns the result of a possible post-increment of operand B
;  after the possible post-increment of A, the storing of the ALU result, etc.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{reg-file-after-oprd-b-post-incre!ment} \\  
\=\+{\rm{reg-file-after-oprd-b-post-increment}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-oprd-b-post-incre!ment} \\ 
$=$$\;\;\;\;${\rm{update-v-nth}}\,(\=\+{\rm{b-indirect-reg-b-inc}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-indirect-reg-b-inc}, \\ 
{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-a-post-increment}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-oprd-a-post-incre!ment}, \\ 
{\rm{v-nat-inc}}\,({\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-a-post-increment}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-oprd-a-post-incre!ment})\-\index{v-nth})\index{v-nat-inc})\-\index{update-v-nth}\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Function SOFT is the programmer's interpreter for FM8501.           ;;
;;          This function completely defines the effect of all instructions     ;;
;;          on the programmer visable state.                                    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


;  This function returns the result of executing n instructions, where
;  n is the length of lst.

\end{verbatim}\begin{tabbing}{\sc Definition}:\index{soft} \\  
\=\+{\rm{soft}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{lst\/}})\index{soft} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{lst\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\rm{list}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}) \\ 
{\bf else }{\rm{soft}}\,(\=\+{\rm{reg-file-after-oprd-b-post-increment}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-oprd-b-post-incre!ment}, \\ 
{\rm{real-mem-after-alu-write}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{real-mem-after-alu-write}, \\ 
{\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-cc-set}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{c}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{c})\-\index{update-v}, \\ 
{\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-cc-set}, \\ 
{\it{v-flag\/}}, \\ 
{\rm{v}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{v})\-\index{update-v}, \\ 
{\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-cc-set}, \\ 
{\it{z-flag\/}}, \\ 
{\rm{bv-to-nat}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}})\-\index{bv-alu-cv-results})\index{bv})\index{bv-to-nat} $\simeq {\tt{0}}$)\-\index{update-v}, \\ 
{\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-cc-set}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{negativep}}\,({\rm{bv-to-tc}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}})\-\index{bv-alu-cv-results})\index{bv})\index{bv-to-tc}))\-\index{update-v}, \\ 
{\rm{cdr}}\,({\it{lst\/}}))\-\index{soft}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Function SOFT-RESET specifies what the programmer sees after        ;;
;;          reset has occured.  Note that SOFT-RESET calls the function         ;;
;;          SOFT.  After a reset, the software instruction interpreter is       ;;
;;          is the function SOFT.                                               ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{soft-reset} \\  
\=\+{\rm{soft-reset}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{oracle\/}})\index{soft-reset} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{oracle\/}} $\simeq\;${{\bf{nil}}}${}$ \\ 
{\bf then }{\rm{list}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}) \\ 
{\bf else }{\rm{soft}}\,(\=\+{\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv})\index{update-nth}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{cdr}}\,({\it{oracle\/}}))\-\index{soft}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          This file contains the events leading up to and including           ;;
;;          the proof that an abstraction, containing the programmer            ;;
;;          visable registers, of BIG-MACHINE is equivalent to SOFT.            ;;
;;          This equivalence is the main result of this work; this result       ;;
;;          proves the correctness of a large piece of hardware with            ;;
;;          respect to a high-level description.                                ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;




;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Help lemmas for proving the correctness of "soft-machine"           ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  a-reg-after-a-b-is-a-value-for-alu-after-oprd-a-pre-decrement \\ \index{a-reg-after-a-b-is-a-value-for-!alu-after-oprd-a-pre-decrement}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b} \\ 
$=$$\;\;\;\;${\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-value-for-alu-after-oprd-a-pre!-decrement})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  b-reg-after-a-b-is-b-value-for-alu-after-oprd-b-pre-decrement \\ \index{b-reg-after-a-b-is-b-value-for-!alu-after-oprd-b-pre-decrement}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b} \\ 
$=$$\;\;\;\;${\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-value-for-alu-after-oprd-b-pre!-decrement})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  hard-c-flag-is-soft-c-flag \\ \index{hard-c-flag-is-soft-c-flag}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{c-flag\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{alu-c-flag}}\,(\=\+{\rm{nth}}\,({\rm{bv-to-nat}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{bv-to-nat}, {\it{real-mem\/}})\index{nth}, \\ 
{\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-value-for-alu-after-oprd-a-pre!-decrement}, \\ 
{\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-value-for-alu-after-oprd-b-pre!-decrement}, \\ 
{\it{c-flag\/}})\-\index{alu-c-flag} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{b-cc-set}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{c}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{c})\-\index{update-v})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  hard-v-flag-is-soft-v-flag \\ \index{hard-v-flag-is-soft-v-flag}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{v-flag\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{alu-v-flag}}\,(\=\+{\rm{nth}}\,({\rm{bv-to-nat}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{bv-to-nat}, {\it{real-mem\/}})\index{nth}, \\ 
{\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-value-for-alu-after-oprd-a-pre!-decrement}, \\ 
{\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-value-for-alu-after-oprd-b-pre!-decrement}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}})\-\index{alu-v-flag} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{b-cc-set}, \\ 
{\it{v-flag\/}}, \\ 
{\rm{v}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{v})\-\index{update-v})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  hard-z-flag-is-soft-z-flag \\ \index{hard-z-flag-is-soft-z-flag}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{z-flag\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{alu-z-flag}}\,(\=\+{\rm{nth}}\,({\rm{bv-to-nat}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{bv-to-nat}, {\it{real-mem\/}})\index{nth}, \\ 
{\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-value-for-alu-after-oprd-a-pre!-decrement}, \\ 
{\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-value-for-alu-after-oprd-b-pre!-decrement}, \\ 
{\it{c-flag\/}}, \\ 
{\it{z-flag\/}})\-\index{alu-z-flag} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{b-cc-set}, \\ 
{\it{z-flag\/}}, \\ 
{\rm{bv-to-nat}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}})\-\index{bv-alu-cv-results})\index{bv})\index{bv-to-nat} $\simeq {\tt{0}}$)\-\index{update-v})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  sizep-a-value-for-alu-after-oprd-a-pre-decrement \\ \index{sizep-a-value-for-alu-after-opr!d-a-pre-decrement}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{size}}\,({\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-value-for-alu-after-oprd-a-pre!-decrement})\index{size} \\ 
$=$$\;\;\;\;${\sc{machine-size}}\index{machine-size})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  hard-n-flag-is-soft-n-flag \\ \index{hard-n-flag-is-soft-n-flag}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{boolp}}\,({\it{n-flag\/}})\index{boolp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{alu-n-flag}}\,(\=\+{\rm{nth}}\,({\rm{bv-to-nat}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{bv-to-nat}, {\it{real-mem\/}})\index{nth}, \\ 
{\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-value-for-alu-after-oprd-a-pre!-decrement}, \\ 
{\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-value-for-alu-after-oprd-b-pre!-decrement}, \\ 
{\it{c-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{alu-n-flag} \\ 
$=$$\;\;\;\;${\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{b-cc-set}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{negativep}}\,({\rm{bv-to-tc}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}})\-\index{bv-alu-cv-results})\index{bv})\index{bv-to-tc}))\-\index{update-v})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  addr-out-after-a-b-is-v-nth-of-reg-file-after-oprd-b-pre-decrement \\ \index{addr-out-after-a-b-is-v-nth-of-!reg-file-after-oprd-b-pre-decrement}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{addr-out-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{addr-out-after-a-b} \\ 
$=$$\;\;\;\;${\rm{v-nth}}\,(\=\+{\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{current-instruction})\index{bv-oprd-b}, \\ 
{\rm{reg-file-after-oprd-b-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-b-pre-decre!ment})\-\index{v-nth})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  hard-real-mem-is-soft-real-mem \\ \index{hard-real-mem-is-soft-real-mem}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{real-mem-thru-post-inc}}\,(\=\+{\rm{nth}}\,({\rm{bv-to-nat}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{bv-to-nat}, {\it{real-mem\/}})\index{nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{nth}}\,(\=\+{\rm{bv-to-nat}}\,({\rm{bv-oprd-b}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{bv-oprd-b})\index{bv-to-nat}, \\ 
{\rm{reg-file-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-oprd-b-pre-decre!ment})\-\index{nth}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-value-for-alu-after-oprd-a-pre!-decrement}, \\ 
{\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-value-for-alu-after-oprd-b-pre!-decrement})\-\index{real-mem-thru-post-inc} \\ 
$=$$\;\;\;\;${\rm{real-mem-after-alu-write}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{real-mem-after-alu-write})\-\-
\end{tabbing}


\begin{tabbing}{\sc Theorem}:  reg-file-after-a-b-is-reg-file-after-oprd-b-pre-decrement \\ \index{reg-file-after-a-b-is-reg-file-!after-oprd-b-pre-decrement}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{reg-file-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-a-b} \\ 
$=$$\;\;\;\;${\rm{reg-file-after-oprd-b-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-b-pre-decre!ment})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  hard-reg-file-is-soft-reg-file \\ \index{hard-reg-file-is-soft-reg-file}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{reg-file-from-alu-thru-post-inc}}\,(\=\+{\rm{nth}}\,(\=\+{\rm{bv-to-nat}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth})\index{bv-to-nat}, \\ 
{\it{real-mem\/}})\-\index{nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{reg-file-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-oprd-b-pre-decre!ment}, \\ 
{\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-value-for-alu-after-oprd-a-pre!-decrement}, \\ 
{\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-value-for-alu-after-oprd-b-pre!-decrement})\-\index{reg-file-from-alu-thru-post-inc} \\ 
$=$$\;\;\;\;${\rm{reg-file-after-oprd-b-post-increment}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-oprd-b-post-incre!ment})\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Oracle generation function for BIG-MACHINE given the oracle         ;;
;;          for SOFT.  The SOFT machine oracle is a list, each element of       ;;
;;          the list contains four arbitrary values.  This values are "fixed"   ;;
;;          into numbers and used to construct a BIG-MACHINE oracle.  These     ;;
;;          four-tuples describe the possible delay when BIG-MACHINE accesses   ;;
;;          memory.  The values are the number of waits to be inserted in       ;;
;;          memory accesses.  The four-tuples meaning is as follows:            ;;
;;                                                                              ;;
;;          (ir-wait fetch-oprd-a-wait fetch-oprd-b-wait store-oprd-b-wait)     ;;
;;                                                                              ;;
;;          ir-wait -- number of wait states for fetching an instruction        ;;
;;          fetch-oprd-a-wait -- number of wait states for fetching OPERAND-A   ;;
;;          fetch-oprd-b-wait -- number of wait states for fetching OPERAND-B   ;;
;;          store-oprd-b-wait -- number of wait states for storing OPERAND-B    ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{oracle} \\  
\=\+{\rm{oracle}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{lst\/}})\index{oracle} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{lst\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\bf{nil}} \\ 
{\bf else }{\rm{append}}\,(\=\+{\rm{state-1-to-1-oracle}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{car}}\,({\rm{car}}\,({\it{lst\/}})), \\ 
{\rm{cadr}}\,({\rm{car}}\,({\it{lst\/}})), \\ 
{\rm{caddr}}\,({\rm{car}}\,({\it{lst\/}})), \\ 
{\rm{cadddr}}\,({\rm{car}}\,({\it{lst\/}})))\-\index{state-1-to-1-oracle}, \\ 
{\rm{oracle}}\,(\=\+{\rm{reg-file-after-oprd-b-post-increment}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-oprd-b-post-incre!ment}, \\ 
{\rm{real-mem-after-alu-write}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{real-mem-after-alu-write}, \\ 
{\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-cc-set}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{c}}\,({\rm{bv-alu-cv-results}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}})\-\index{bv-alu-cv-results})\index{c})\-\index{update-v}, \\ 
{\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-cc-set}, \\ 
{\it{v-flag\/}}, \\ 
{\rm{v}}\,({\rm{bv-alu-cv-results}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}})\-\index{bv-alu-cv-results})\index{v})\-\index{update-v}, \\ 
{\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-cc-set}, \\ 
{\it{z-flag\/}}, \\ 
{\rm{bv-to-nat}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}})\-\index{bv-alu-cv-results})\index{bv})\index{bv-to-nat} $\simeq {\tt{0}}$)\-\index{update-v}, \\ 
{\rm{update-v}}\,(\=\+{\rm{b-cc-set}}\,({\rm{current-instruction}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{current-instruction})\index{b-cc-set}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{negativep}}\,({\rm{bv-to-tc}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}})\-\index{bv-alu-cv-results})\index{bv})\index{bv-to-tc}))\-\index{update-v}, \\ 
{\rm{cdr}}\,({\it{lst\/}}))\-\index{oracle})\-$\;${\bf  endif}\-\-
\end{tabbing}


\begin{tabbing}{\sc Definition}:\index{big-machine-induction} \\  
\=\+{\rm{big-machine-induction}}\,(\=\+{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\it{lst\/}})\-\index{big-machine-induction} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{lst\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\bf{t}} \\ 
{\bf else }{\rm{big-machine-induction}}\,(\=\+$\neg$ {\rm{b-store-alu-result}}\,(\=\+{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth})\-\index{b-store-alu-result}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\rm{reg-file-from-alu-thru-post-inc}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{reg-file-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-a-b}, \\ 
{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b})\-\index{reg-file-from-alu-thru-post-inc}, \\ 
{\rm{addr-out-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{addr-out-after-a-b}, \\ 
{\rm{alu-c-flag}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}})\-\index{alu-c-flag}, \\ 
{\rm{alu-v-flag}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}})\-\index{alu-v-flag}, \\ 
{\rm{alu-z-flag}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\it{z-flag\/}})\-\index{alu-z-flag}, \\ 
{\rm{alu-n-flag}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{alu-n-flag}, \\ 
{\rm{a-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-reg-after-a-b}, \\ 
{\rm{v-nth}}\,({\rm{nth}}\,({\tt{0}}, {\it{reg-file\/}})\index{nth}, {\it{real-mem\/}})\index{v-nth}, \\ 
{\rm{trunc}}\,({\sc{default-visual-mem-value}}\index{default-visual-mem-value}, {\tt{16}})\index{trunc}, \\ 
{\rm{real-mem-thru-post-inc}}\,(\=\+{\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{addr-out-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{addr-out-after-a-b}, \\ 
{\it{real-mem\/}}, \\ 
{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b})\-\index{real-mem-thru-post-inc}, \\ 
{\rm{watch-dog}}\,(\=\+{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\rm{bv}}\,({\rm{bv-alu-cv}}\,(\=\+{\rm{a-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{a-reg-after-a-b}, \\ 
{\rm{b-reg-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{b-reg-after-a-b}, \\ 
{\it{c-flag\/}}, \\ 
{\rm{bv-alu-op-code}}\,({\rm{v-nth}}\,(\=\+{\rm{nth}}\,(\=\+{\tt{0}}, \\ 
{\it{reg-file\/}})\-\index{nth}, \\ 
{\it{real-mem\/}})\-\index{v-nth})\index{bv-alu-op-code})\-\index{bv-alu-cv})\index{bv}, \\ 
{\rm{addr-out-after-a-b}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{addr-out-after-a-b})\-\index{watch-dog}, \\ 
{\rm{cdr}}\,({\it{lst\/}}))\-\index{big-machine-induction}$\;${\bf  endif}\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Abstraction for looking at certian registers in BIG-MACHINE.        ;;
;;          Specifically, the definition below allows us to view the registers  ;;
;;          REG-FILE, REAL-MEM, C-FLAG, V-FLAG, Z-FLAG, and N-FLAG, which       ;;
;;          are the registers used in SOFT machine.                             ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{abstract} \\  
\=\+{\rm{abstract}}\,({\it{m\/}})\index{abstract} \\ 
$=$$\;\;\;\;${\rm{list}}\,(\=\+{\rm{cadddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{cadddddddddddr}}\,({\it{m\/}}), \\ 
{\rm{caddddddddddddr}}\,({\it{m\/}}))\-\-
\end{tabbing}           \begin{verbatim}; n-flag

\end{verbatim}\begin{tabbing}{\sc Theorem}:  abstract-list \\ \index{abstract-list}
\=\+(\=\+{\rm{abstract}}\,({\rm{list}}\,(\=\+{\it{mar\/}}, \\ 
{\it{read\/}}, \\ 
{\it{write\/}}, \\ 
{\it{dtack\/}}, \\ 
{\it{reset\/}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}})\-)\index{abstract} \\ 
$=$$\;\;\;\;${\rm{list}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}))\- \\ 
$=$$\;\;\;\;${\bf{t}}\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          The following lemmas ensure SOFT machine does not change the        ;;
;;          size of any registers.                                              ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Theorem}:  ramp-reg-file-after-oprd-a-pre-decrement \\ \index{ramp-reg-file-after-oprd-a-pre-!decrement}
\=\+(\=\+({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{every-member-sizep}}\,(\=\+{\rm{reg-file-after-oprd-a-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-oprd-a-pre-decre!ment}, \\ 
{\it{m\/}})\-\index{every-member-sizep} \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{length}}\,({\rm{reg-file-after-oprd-a-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-a-pre-decre!ment})\index{length} \\ 
$=$$\;\;\;\;${\tt{8}})\-)\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-reg-file-after-oprd-b-pre-decrement \\ \index{ramp-reg-file-after-oprd-b-pre-!decrement}
\=\+(\=\+({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{every-member-sizep}}\,(\=\+{\rm{reg-file-after-oprd-b-pre-decrement}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}})\-\index{reg-file-after-oprd-b-pre-decre!ment}, \\ 
{\it{m\/}})\-\index{every-member-sizep} \\ 
$\wedge$$\;\;\;\;$(\=\+{\rm{length}}\,({\rm{reg-file-after-oprd-b-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{reg-file-after-oprd-b-pre-decre!ment})\index{length} \\ 
$=$$\;\;\;\;${\tt{8}})\-)\-\-
\end{tabbing}
 

\begin{tabbing}{\sc Theorem}:  size-bv-alu-cv-results \\ \index{size-bv-alu-cv-results}
\=\+{\rm{size}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\index{size} \\ 
$=$$\;\;\;\;${\rm{size}}\,({\rm{a-value-for-alu-after-oprd-a-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{a-value-for-alu-after-oprd-a-pre!-decrement})\index{size}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-reg-file-after-oprd-b-post-increment \\ \index{ramp-reg-file-after-oprd-b-post!-increment}
\=\+(\=\+({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;${\rm{ramp}}\,(\=\+{\rm{reg-file-after-oprd-b-post-increment}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{reg-file-after-oprd-b-post-incre!ment}, \\ 
{\it{m\/}}, \\ 
{\tt{8}})\-\index{ramp}\-
\end{tabbing}



\begin{tabbing}{\sc Theorem}:  sizep-b-value-for-alu-after-oprd-b-pre-decrement \\ \index{sizep-b-value-for-alu-after-opr!d-b-pre-decrement}
\=\+(\=\+{\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{size}}\,({\rm{b-value-for-alu-after-oprd-b-pre-decrement}}\,({\it{reg-file\/}}, {\it{real-mem\/}})\index{b-value-for-alu-after-oprd-b-pre!-decrement})\index{size} \\ 
$=$$\;\;\;\;${\sc{machine-size}}\index{machine-size})\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-real-mem-after-alu-write \\ \index{ramp-real-mem-after-alu-write}
\=\+(\=\+({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) \\ 
$\wedge$$\;\;\;\;$({\it{x\/}} $=$ {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp}) \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} \\ 
$\wedge$$\;\;\;\;${\rm{ramp}}\,({\it{real-mem\/}}, {\sc{machine-size}}\index{machine-size}, {\rm{exp}}\,({\tt{2}}, {\sc{machine-size}}\index{machine-size})\index{exp})\index{ramp})\- \\ 
$\rightarrow$$\;\;\;\;${\rm{ramp}}\,(\=\+{\rm{real-mem-after-alu-write}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}})\-\index{real-mem-after-alu-write}, \\ 
{\it{m\/}}, \\ 
{\it{x\/}})\-\index{ramp}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  size-nth \\ \index{size-nth}
({\rm{ramp}}\,({\it{lst\/}}, {\tt{16}}, {\it{n\/}})\index{ramp} $\wedge$ ({\it{i\/}} $<$ {\it{n\/}})) $\rightarrow$ ({\rm{size}}\,({\rm{nth}}\,({\it{i\/}}, {\it{lst\/}})\index{nth})\index{size} $=$ {\tt{16}})
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          The proof of equivalence between the hardware definition of         ;;
;;          FM8501 and the software definition of FM8501.  This lemma proves    ;;
;;          that BIG-MACHINE executes instructions in the same way as the       ;;
;;          interpreter SOFT.                                                   ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;       


\end{verbatim}\begin{tabbing}{\sc Theorem}:  big-machine-is-soft-machine \\ \index{big-machine-is-soft-machine}
\=\+(\=\+({\it{mar1\/}} $=$ {\rm{nat-to-bv}}\,({\tt{1}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{standard-hyps}}\,(\=\+{\it{mar1\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}})\-\index{standard-hyps})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{abstract}}\,({\rm{big-machine}}\,(\=\+{\it{mar1\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{watch-dog\/}}, \\ 
{\rm{oracle}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{lst\/}})\-\index{oracle})\-\index{big-machine})\index{abstract} \\ 
$=$$\;\;\;\;${\rm{soft}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{lst\/}})\index{soft})\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          The following events are concerning with the programmer's view      ;;
;;          of FM8501 during a reset operation.                                 ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


\end{verbatim}\begin{tabbing}{\sc Definition}:\index{oracle-reset} \\  
\=\+{\rm{oracle-reset}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{lst\/}})\index{oracle-reset} \\ 
$=$$\;\;\;\;$\=\+{\bf if }{\it{lst\/}} $\simeq\;${{\bf{nil}}}${}$$\;\;${\bf then }{\bf{nil}} \\ 
{\bf else }{\rm{append}}\,(\=\+{\rm{state-0-to-0-wait-to-1-oracle}}\,({\rm{car}}\,({\rm{car}}\,({\it{lst\/}})))\index{state-0-to-0-wait-to-1-oracle}, \\ 
{\rm{oracle}}\,(\=\+{\rm{update-nth}}\,(\=\+{\bf{t}}, \\ 
{\tt{0}}, \\ 
{\it{reg-file\/}}, \\ 
{\rm{nat-to-bv}}\,({\tt{0}}, {\sc{machine-size}}\index{machine-size})\index{nat-to-bv})\-\index{update-nth}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\rm{cdr}}\,({\it{lst\/}}))\-\index{oracle})\-$\;${\bf  endif}\-\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  ramp-reg-file-after-reset \\ \index{ramp-reg-file-after-reset}
\=\+({\rm{ramp}}\,({\it{reg-file\/}}, {\sc{machine-size}}\index{machine-size}, {\tt{8}})\index{ramp} $\wedge$ ({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size})) \\ 
$\rightarrow$$\;\;\;\;${\rm{ramp}}\,({\rm{update-nth}}\,({\bf{t}}, {\tt{0}}, {\it{reg-file\/}}, {\rm{nat-to-bv}}\,({\tt{0}}, {\it{m\/}})\index{nat-to-bv})\index{update-nth}, {\it{m\/}}, {\tt{8}})\index{ramp}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  sizep-trunc-at-machine-size \\ \index{sizep-trunc-at-machine-size}
({\it{m\/}} $=$ {\sc{machine-size}}\index{machine-size}) $\rightarrow$ {\rm{sizep}}\,({\rm{trunc}}\,({\it{x\/}}, {\it{m\/}})\index{trunc}, {\it{m\/}})\index{sizep}
\end{tabbing}


\begin{verbatim};  Proof that reseting FM8501 sets register 0 to zero.

\end{verbatim}\begin{tabbing}{\sc Theorem}:  soft-reset-works \\ \index{soft-reset-works}
\=\+(\=\+({\it{mar0\/}} $=$ {\rm{nat-to-bv}}\,({\tt{0}}, {\sc{nxsz}}\index{nxsz})\index{nat-to-bv}) \\ 
$\wedge$$\;\;\;\;${\rm{standard-hyps}}\,(\=\+{\it{mar0\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}})\-\index{standard-hyps})\- \\ 
$\rightarrow$$\;\;\;\;$(\=\+{\rm{abstract}}\,({\rm{big-machine}}\,(\=\+{\it{mar0\/}}, \\ 
{\bf{f}}, \\ 
{\bf{f}}, \\ 
{\it{dtack\/}}, \\ 
{\bf{t}}, \\ 
{\it{no-store\/}}, \\ 
{\it{data-out\/}}, \\ 
{\it{reg-file\/}}, \\ 
{\it{addr-out\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{a-reg\/}}, \\ 
{\it{b-reg\/}}, \\ 
{\it{i-reg\/}}, \\ 
{\it{visual-mem\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{memory-watch-dog-history\/}}, \\ 
{\rm{oracle-reset}}\,(\=\+{\it{reg-file\/}}, \\ 
{\it{real-mem\/}}, \\ 
{\it{c-flag\/}}, \\ 
{\it{v-flag\/}}, \\ 
{\it{z-flag\/}}, \\ 
{\it{n-flag\/}}, \\ 
{\it{lst\/}})\-\index{oracle-reset})\-\index{big-machine})\index{abstract} \\ 
$=$$\;\;\;\;${\rm{soft-reset}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}}, {\it{v-flag\/}}, {\it{z-flag\/}}, {\it{n-flag\/}}, {\it{lst\/}})\index{soft-reset})\-\-
\end{tabbing}

\begin{verbatim};;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                              ;;
;;          Flag interpretation lemmas                                          ;;
;;                                                                              ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

\end{verbatim}
\noindent{\sc Event}:   Disable bv-alu-cv-results.

\addvspace{18pt}

\begin{tabbing}{\sc Theorem}:  bit-vector-interpretation-of-z-flag \\ \index{bit-vector-interpretation-of-z-!flag}
\=\+({\rm{bv-to-nat}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\index{bv-to-nat} $\simeq {\tt{0}}$) \\ 
$=$$\;\;\;\;${\rm{v-zerop}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\index{v-zerop}\-
\end{tabbing}

\begin{tabbing}{\sc Theorem}:  integer-interpretation-of-z-flag \\ \index{integer-interpretation-of-z-fla!g}
\=\+({\rm{bv-to-nat}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\index{bv-to-nat} $\simeq {\tt{0}}$) \\ 
$=$$\;\;\;\;$({\tt{0}} $=$ {\rm{bv-to-tc}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\index{bv-to-tc})\-
\end{tabbing}



\begin{tabbing}{\sc Theorem}:  bit-vector-interpretation-of-n-flag \\ \index{bit-vector-interpretation-of-n-!flag}
\=\+{\rm{negativep}}\,({\rm{bv-to-tc}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\index{bv-to-tc}) \\ 
$=$$\;\;\;\;${\rm{bitn}}\,(\=\+{\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv}, \\ 
{\rm{size}}\,({\rm{bv}}\,({\rm{bv-alu-cv-results}}\,({\it{reg-file\/}}, {\it{real-mem\/}}, {\it{c-flag\/}})\index{bv-alu-cv-results})\index{bv})\index{size})\-\index{bitn}\-
\end{tabbing}






%\end{list}
\printindex
\end{document}
