Computer Architecture Seminar Abstracts

Fall 2007

Maurice Herlihy
Brown University

Transactional Boosting: A Methodology for Highly-Concurrent Transactional Objects


We describe a methodology for transforming a large class of highly-concurrent linearizable objects into highly-concurrent transactional objects. As long as the linearizable implementation satisfies certain regularity properties (informally, that every method has an inverse), we define a simple wrapper for the linearizable implementation that guarantees that concurrent transactions without inherent conflicts can synchronize at the same granularity as the original linearizable implementation.


Maurice Herlihy received an A.B. degree in Mathematics from Harvard University and a Ph.D. degree in Computer Science from MIT. He has been an Assistant Professor in the Computer Science Department at Carnegie Mellon University, a member of the research staff at Digital Equipment Corporation's Cambridge (MA) Research Lab, and a consultant for Sun Microsystems. He is now a Professor of Computer Science at Brown University.

Prof. Herlihy's research centers on practical and theoretical aspects of multiprocessor synchronization, with a focus on wait-free and lock-free synchronization. His 1991 paper "Wait-Free Synchronization" won the 2003 Dijkstra Prize in Distributed Computing, and he shared the 2004 Goedel Prize for his 1999 paper "The Topological Structure of Asynchronous Computation." He is a Fellow of the ACM.

Greg Grohoski
Distinguished Engineer
Sun Microsystems

Sun's UltraSparc T2: A Highly-Threaded Server-on-a-Chip


Sun's UltraSparc T2 is a server-on-a-chip designed for high throughput and low power. It contains 64 threads, wire-speed cryptography for the two embedded 10 GB Ethernet ports, massive memory bandwidth, and advanced virtualization capabilities. Mr. Grohoski will give a technical overview of the design and present some benchmark results.


Mr. Grohoski is a Distinguished Engineer at Sun Microsystems' Austin Design Center. He coarchitected and led RTL development of the UltraSparc T2 core. Prior to Sun, Mr. Grohoski co-founded a startup, Digital Archway, and served as the VP of Hardware Development. Previously, he worked at Intel, Cyrix, and IBM, where he was a principal designer of the IBM RS/6000 and Power2. Mr. Grohoski holds a BSEE from Cornell and an MSEE from the University of Illinois at Urbana-Champaign.

Vijay Pai
Purdue University

Hardware and Software Support for Parallel Network Services


Although multicore processors are now pervasive, the performance of such systems depends entirely on the ability of the target applications to exploit parallelism. This talk first presents Aspen, a parallel programming language and runtime system that currently targets network service applications. Aspen programs resemble task flowcharts, with the nodes being instances of computational modules and the edges being unidirectional communication channels. Aspen automatically and transparently supports task-level parallelism among module instances and data-level parallelism across different flows in an application or, in some cases, across different work items within a flow. Aspen adaptively allocates threads to modules according to the dynamic workload seen at those modules. Experimental results indicate performance competitive with (and sometimes better than) current server programming models while using 54-96% fewer lines of user code.

This talk also presents LineSnort, a self-securing programmable Ethernet controller. LineSnort parallelizes the Snort network intrusion detection system (NIDS) using concurrency across TCP sessions and executes those parallel tasks on multiple low-frequency/low-power RISC cores. LineSnort additionally exploits opportunities for intra-session concurrency based on domain-specific characteristics of NIDS. The system includes dedicated hardware for high-bandwidth data transfers and for high-performance string matching. Detailed simulation results show that LineSnort can achieve intrusion detection throughputs in excess of 1 Gbps for fairly large rule sets, thus offloading the computationally difficult task of intrusion detection from a server's host CPU and enabling protection against both external and LAN-based attacks.

This talk includes research performed jointly with Derek Schuff, Gautam Upadhyaya, and Sam Midkiff.


Vijay S. Pai received a BSEE degree in 1994, an MS degree in Electrical and Computer Engineering in 1997, and a Ph.D. degree in Electrical and Computer Engineering in 2000, all from Rice University. He joined the faculty of Purdue University in August 2004. Prior to that, he had served as an assistant professor at Rice University (2001-2004) and as a senior developer at iMimic Networking (1999-2001). He received the NSF CAREER award in 2003 and Purdue's Wilfred "Duke" Hesselberth Award for Teaching Excellence in 2007.