System-Level Design of Embedded Platform Architectures
The heterogeneous and distributed nature of many emerging classes of embedded applications adds a new level of design complexity requiring the deployment of tightly-interactive, concurrent processes on networked platform architectures. While the design of a single component is important, the critical challenges in the realization of a system-on-chip or a distributed embedded system lie in the integration of the components. In addressing these challenges we sustain that communication plays an increasingly central role both at design time and run time. We present a communication-based system-level design methodology that simplifies the integrated design and validation of embedded platform architectures while enabling important properties like modularity, scalability, flexibility, and reusability. In particular, we argue how effective design space exploration can be achieved through the decoupling of the design of the computational elements and the synthesis of the communication infrastructure. For the latter we present recent results on the design and optimization of networks-on-chip.
Luca Carloni is an Associate Professor of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree Summa cum Laude in Electronics Engineering from the University of Bologna, Italy, and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley. Luca received the Faculty Early Career Development (CAREER) Award from the National Science Foundation in 2006 and was selected as an Alfred P. Sloan Research Fellow in 2008. At Berkeley Luca was the 2002 recipient of the Demetri Angelakos Memorial Achievement Award in recognition of altruistic attitude towards fellow graduate students. His research interests include methodologies and tools for multi-core system-on-chip platforms with emphasis on system-level design and communication synthesis, design and optimization of networks-on-chip, and distributed embedded systems design. In these areas he has co-authored over sixty-five papers in peer-reviewed journals and conferences. He is an associate editor of the ACM Transactions in Embedded Computing Systems and currently serves as program co-chair of the International Conference on Embedded Software (EMSOFT) and the International Symposium on Networks-on-Chip (NOCS).
How CMOS Scaling Will Affect Architectures and Applications
We are reaching the end stages of Moore’s Law for CMOS. After decades of proportional scaling, imbalances are emerging that provide both peril and opportunity going forward. In this talk, I will describe how CMOS scaling is likely to affect both processors and memory systems, and the implications for future systems. As an illustrative example, scaling imbalances will drive the emergence of resistive memories, which will replace Flash and DRAM, and which will create new challenges for architects. Of these resistive memories, Phase-Change Memory is the closest to commercial adoption, but has the challenge of early and frequent failures of memory cells. I will show how Error-Correcting Pointers (ECP), invented at Microsoft Research, are likely to replace Error-Correcting Codes (ECC) for these resistive memories. With these techniques and others, we may eventually reach terabytes of non-volatile storage in mobile devices. I will conclude with a description of the SONGO system, where we built a web index cache on a mobile phone to use these massive capacities to reduce mobile search latencies.
Doug Burger is Director of Client and Cloud Applications research at Microsoft Research, where he also manages the computer architecture group. He is also an Adjunct Professor at The University of Texas at Austin, where he taught on the faculty from 1999-2008. His research interests span processor architectures, memory systems, mobile devices, cloud computing, new semiconductor technologies, and human/computer interfaces. At UT-Austin, he co-led the TRIPS project with Steve Keckler and Kathryn McKinley. His current main project in MSR is called Natural Computing.
Programming interfaces for manycore hardware as seen from a graphics perspective
We are in the midst of the most exciting period in computer architecture in many years. The rising importance of power efficiency and the increasing challenges to improving single-threaded performance are leading industry to adopt manycore parallelism in virtually all markets and to integrate special-function hardware along with general-purpose computation. But in this new world, it is not yet clear what the abstraction layers between the application and the hardware will ultimately look like, and what hardware capabilities are needed to support the new abstractions. Answering these questions requires a deep understanding of the interaction between the application, the programming model, and the hardware.
In this talk, I will examine the current state of this evolution as illustrated by the data-parallel-oriented DirectCompute and OpenCL programming interfaces. For example, these interfaces support global atomic operations in ways that are amenable to certain kinds of hardware acceleration. I'll also discuss some of the limitations of these interfaces, and provide application examples from graphics workloads that motivate the need for more flexible interfaces in the future.
Bill Mark leads the advanced graphics research group at Intel. Prior to joining Intel he was on the computer sciences faculty at the University of Texas at Austin, where his group investigated flexible real-time 3D graphics techniques and architectures. From 2001-2002 Bill worked at NVIDIA as the technical lead for the design of the Cg language. Bill received his Ph.D. from the University of North Carolina at Chapel Hill and did postdoctoral research at Stanford University.