The principal investigators of this effort are Dr. Doug Burger and Dr. Stephen W. Keckler, two professors of computer architecture hired by the Department of Computer Sciences at the University of Texas at Austin in 1998.
Over the next decade, silicon manufacturing technology will have a tremendous impact on the design and implementation of microprocessors. The ability to place a billion transistors on a single chip offers both unparalleled opportunities and significant challenges. Even though transistors are becoming smaller and faster, the wires that connect them are becoming much slower. With future latencies of tens or eventually hundreds of cycles to cross a single chip, the primary challenge for designers is to exploit the large transistor budgets while minimizing the effects of long on-chip communication delays. At CART, we will investigate these and related issues, which include the following: what is the right granularity at which processing cores (and associated memory banks) are distributed across the chip; what architectural support can mitigate the effects of high-latency on-chip communication; how can software assist in mapping data, computation, and communication onto various regions of a chip; what is the most efficient way for the hardware to break a program into region-based "datathreads" (dynamic parallelization), and can specialized units accelerate key workloads enough to be included on a chip.
Embedded microprocessors account for the majority of processors sold in the market today, and with the advent of "ubiquitous computing," they will proliferate into substantially more applications. With their greater sensitivity to power and area, these processors have very different design constraints high-performance microprocessors. Embedded processors are also often dedicated to a smaller range of workloads than their high-performance counterparts. CART will explore how both price and power may be conserved by designing computational engines specifically for key individual workloads, such as voice recognition. This effort may result either in auxiliary units to assist the embedded processor, or in the incorporation of novel mechanisms into the embedded core itself.
As VLSI technology grows more important in determining an architecture's performance, the evaluation methodology must grow to encompass VLSI and circuit issues. The vast majority of performance analysis done today by academic architecture researchers is at the level of functional software simulation, and does not consider these issues. Furthermore, the complexity of today's (and tomorrow's) microprocessors makes the development of even functional software tools expensive, prohibitively so in many cases. At CART, our goal is to develop a suite of architecture evaluation tools that includes hardware models at various levels of detail. These will enable us to validate our software simulators, consider device-level behavior in our performance models, and perform prototyping (as necessary). We eventually hope to release these tools to the benefit of the entire architecture research community.
CART will have a strong emphasis on experimental computer system research. The faculty and students in the laboratory will develop architectural simulators, implement applications, and design and build prototype chips and systems as necessary to evaluate the architectures. Low-level implementation (whether it be RTL or actual silicon) is vital because silicon technology provides a set of fundamental constraints on computer systems -- proposed architectures that ignore it run the risk of potential irrelevance. Two laboratories are planned: one for application development and simulation, and one for low-level design testing and prototyping. The software laboratory will need computation engines for architectural simulation, logical simulation, circuit simulation, and graphical EDA tools for chip and board level design. In addition, the CART hardware lab will be equipped with logic analyzers, oscilloscopes, signal generators, and other tools necessary for hardware system prototyping.