CART Research Projects
TRIPS
Over the next decade, silicon manufacturing technology will have a
tremendous impact on the design and implementation of microprocessors.
The ability to place a billion transistors on a single chip offers
both unparalleled opportunities and significant challenges. Even
though transistors are becoming smaller and faster, the wires that
connect them are becoming much slower. With future latencies of tens
or eventually hundreds of cycles to cross a single chip, the primary
challenge for designers is to exploit the large transistor budgets
while minimizing the effects of long on-chip communication delays. At
CART, we will investigate these and related issues, which include the
following: what is the right granularity at which processing cores
(and associated memory banks) are distributed across the chip; what
architectural support can mitigate the effects of high-latency on-chip
communication; how can software assist in mapping data, computation,
and communication onto various regions of a chip; what is the most
efficient way for the hardware to break a program into region-based
"datathreads" (dynamic parallelization), and can specialized units
accelerate key workloads enough to be included on a chip.
TRIPS project
TRIPS prototype
TRIPS system software
TFLEX architecture
The TFLEX Microarchitecture -- coming soon.