CS310 Spring 2007

Schedule, Handouts, and Reading

Extras of Handouts are always outside my office, TAY 4.136
 
Week
Date
Lec #
Topic 
Reading FOR this date 
Out
In
(Due)
1
1/17
L1
UT Cancelled 
   

1/18
D1
UT Cancelled
 
 

1/19
L2 Handout #0: Motivation for this course:  to be covered later in the semester:  
To read Handout #0's paper: Detection and prevention of stack buffer overflow attacks, published in Communications of the ACM, Nov 2005.  Go here:  http://www.lib.utexas.edu/indexes/titles.html?let=A
then click on  ACM, and enter the title.
and
Handout #1: Course Operations
Handout #2: Overview Slides (4 on 1 pg)

Discuss:
Introduction to this unusual and fun course

Computer System Abstractions
Patt &Patel Ch 1,

Supplemental reading on:
positional notation,
bases,
base conversion,



   
2
1/22
L3
Handout #3: Data Representation Slides (4 on 1pg)

Discuss: Overview
Wrap-up Overview, focusing on the compiler, ISA, and the micro-architecture.

Yale Patt's "Performance triangle":  The most significant three attributes that contribute to improving the performance:  the algorithm, the compiler, and the microarchitecture (but it has to provide significant parallelism).

FOR FUN:  Browse Patt's short position paper: Microarchitecture, Compilers, and Algorithms from ACM Computing Surveys (CSUR) archive
 Volume 28 ,  Issue 4es  (December 1996) 
 Special issue: position statements on strategic directions in computing research.  (Some of the topics that he references are topics of CS352.)

Discuss: intro to Data Representation
  • Computer system basics: digital vs. analog?
  • If digital, then which base to choose?
  • If binary, all information is encoded in bits.
  • What are the encoding  algorithms and why?  Focus on numeric values
Overview P&P: focus on 1.7

Data Representation 2.1-2.2, Hdt #3

For fun: 
The history of the term "bit" from IEEE Annals of History of Computing

 

1/24
L4
Handout #4: Supplement on Data Representation (Oops: the copier ran out of staples, so anyone attending the 11a.m. lecture may not have both pages (4 sides).  Extra copies are outside my office.)

Discuss: Data Representation
  • Two strategies for encoding data, ie. rep(x):
    1. Mathematical formula requires the decimal-to-binary function d2b() for non-negative values
    2. Strategic assignment of arbitrary values
  • ALL ENCODINGS are dramatically influenced by the "operations" on the encoded data.
  • Sign Magnitude, 1's complement, 2's complement
Data Representation 2.2, 2.3, 2.7.4, 2.7.3 (and pg441)

(Note: 2.4  describes only conversions between decimal and a 2's complement encoding of signed integers) 
   

1/25
D2
Discuss:
  • Practice conversions of base 10 integers to base 2, 16, and 8 (and vice versa). Note - we are starting off with "non-negative integers". You need to get fast at the conversions, particularly between base2 and base16.
  • Build a table given nbits, and multiple signed integer strategies; compare the differences between the columns, as to which values are represented by the same encoding.
  • Specifying the max and min values, for n-bits
  • Design algorithms to convert from the binary encoding of a signed integer back to it's decimal value.
Notes, including the additive inverse.

 

1/26
L5
Handout #5:  Data Representation Slides (4 on 1pg)
Discuss: Data Representation
Wrap-up signed integers: 2's complement (the theory of why it works, using mod2n), motivation for the excess signed integer strategy, and BCD.
Why we use Hex digits, but debuggers never indicate the "minus" sign.

Character and String representatons: Notes on Strings
Mystery Question #1 (MQ1): What is the purpose of the Parity Bit?  And how do you calculate the "parity bit's" value, given the "odd parity" strategy".  Write your answer in 25-50 words and hand it in only on Lecture 6 (for .5%)
additional reading:
Supplement Handout #4, 2.5, 2.6

 HW1



MQ1
 
3
1/29
L6
Handout #6: Transistor Slides (4 on  1pg)
Handout #7: Transistors Supplement (not online)
Discuss:
  • Announcements, Career Fair, Linux, FAQ, Mystery Question...
  • Motivation for Floating Point  Data Type
  • "the lowest level":  The current "device" is a Transistor
Floating Point data representation
Supplement on
Floating Point
,
P/P 2.7.2

Transistors
3.1, Supplement on Transistors

Story on Intel's New 45nm Transistor> (i.e. the last 3 pages of Handout 7, without photos of the 2 transistors)

MQ1

1/31
L7
Discuss: Transistor components and building simple logic gates: AND, OR, NOT, XOR, NAND, NOR.
3.1-3.2
   

2/1
D3
Discuss:
Floating Point practice
Bitwise Operators:  focus on AND
Transistor Practice
Build a logic circuit with transistors
Notes on the above topics.
the and bitwise operator and "the bit- mask" 
2.6

java's  shift operator: >>>
See wikipedia's logical shift

3.1-3.2
   

2/2
L8
Handout #8: CombLogicSlides (4 on  1pg)
Handout #9: Addition/Subtraction Slides (4 on  1pg)
Discuss: Wrap-up Transistors (Device Level)
Circuits: Logic Gates
Circuits: Combinational Logic: n-bit Ripple Carry Adder, and the 1bit Full Adder.
3.3, 2.5
HW2  Hw1
4
2/5
L9
Discuss: Addition/Subtraction for 2's comp signed integers and for unsigned integers
Decoders, Multiplexors
Mystery Question #2 (MQ2):  Due Wed 2/7 in class.  Who is Claude Shannon?  What is he known for?  Browse his Master's thesis! What is its contribution?  Lastly, goto the pdf page 62 (his page 59)... what combinational logic is he designing?  (Your answer should be 25-50 words.)
3.3, 3.4  MQ2  

2/7
L10
Handout #10: Storage Elements Slides (4 on 1pg)
Discuss: Storage Elements
3.3    MQ2

2/8
D4
Discuss:
HW2 Questions, Review
Signed Integer Addition, Subtraction, Overflow
Unsigned Integer addition, subtraction, Overflow/Underflow.
Multiplexors
Notes on the above topics.
     

2/9
L11
Handout #11: Memory Slides (4 on 1pg)
Discuss: Storage Elements & Memory
  • Review the ALU and multiplexor
  • Gated-D Latch: Controlling the R-S Latch
  • A simple 4bit stored value
  • Storage in the CPU: Registers, a temporary storage for your programs
  • Memory
3.4

memory topics:
3.5
   
5
2/12
L12
Handout #12: Memory Supplement
Discuss: Memory and Multi-byte values
  • Multi-byte addresses
  • Multi-byte ordering between a CPU and a register:  "endianness"
  • Alignment: What are the preferred addresses of a multi-byte quantity (in order to have the best performance)
3.5,
Memory Supplement

 HW2

2/14
L13
Handout #13: Sequential Logic (FSM) Slides (4 on 1pg)
Discuss: Finite State Machine (FSM)


Wrapup:  CPU's Datapath with Combinational Logic examples, Storage Elements, and a FSM, and a simple memory.
3.6, 3.7
HW3  

2/15
D5
Handout #14: Partial Solutions to Hmwk1Q123 (not online)

Practice on:
  • Storage Elements, including the Master Slave
  • Memory
  • Finite State Machine
Notes on the above topics.
     

2/16
L14
Handout #15: Memory Reading: ROM, RAM, and Memory Hierarchy Supplement (not online)
Handout #16: MicroArchitecture/Instruction Cycle Slides (4 on 1pg)
Handout #17: Introduction to the ISA Supplement, not online)
Discuss: MicroArchitecture
  • Review FSM and Master-Slave  Flip-flop
  • MicroArchitecture for the LC3
  • "Von Neumann" model (aka Eckert/Mauchly...)
  • CPU <--> Memory Interface (MAR, MDR)
  • Instruction Cycle
Handout #15,
4.1-4.2
   
6
2/19
L15
Discuss: ISA
  • Instruction Cycle: fetch, decode, execute...
  • Exploring the LC-3 datapath for the ADD instruction


4.3, 4.4 (ignore the LDR and JMP details)
   

2/21
L16
Handout #18: ISA Taxonomy#1 Slides (4 on 1pg)
Handout #19: Partial Solution to Hmwk2 (not online)
Handout #20: Exam 1 Objectives
Discuss: ISA Taxonomy of operands
Handout #17, Handout #18
Ch 5.1
   

2/22
D6
Practice:
  • General Questions on HW3
  • Exam Topics
  • Memory Hierarchy: motivation and concept of "Locality of Reference". (See Handout#15: Supplement on Memory Hierarchy and ROM/RAM)
  • Patt/Patel problem 4.10 for the ADD instruction only. (Add another row to the table with the label: Register File (R0-R7). For each phase of the ADD instruction, identify the register that is written and mark the corresponding cell in the table.
     

2/23
L17
News: Study Quiz1 (a 10 minute activity to give you feedback, before the exam)
Handout #21: Solutions to Hmwk3 (not online)
Discuss: Study Quiz 1 Answers
Discuss Solutions to Hmwk3
Extra Copies of Handouts that are not online are outside TAY 4.136.
EXAM 1 review
  10:30
HW3
no
late
hw's
7
2/26
L18
Yes, we'll have class on Monday:
  • Last minute questions on the exam
  • Continuing with ISA taxonomy
Handout #17,
Ch 5.2
   

2/26
EX1
Exam #1: 7-9:30pm




2/28
L19
Handout #22:
  front: LC-3 reference,
  back: LC3 Program 1 worksheet
Handout #23: LC3 ISA and intro to ASM Language Slides (4 on 1pg)
Discuss: LC-3 ISA  and Introduction to the LC-3 Assembly Language
Ch 5.1-5.2, 7.1-7.2.2, and Appendix A3 (for ADD, AND, NOT, LD, LEA, ST, BRcc, and TRAP). 
 

3/1
D7
Discuss: Focus on the LC-3 ISA and assembly language statements, and practice compiling HLL code into asm. language:
  • You are the compiler, generating the code for the Example on Handout #22: i.e you will finish writing the assembly language for (LC-3 Program 1 worksheet)
  • Discuss the Assembler Directives, Pseudo instructions, and questions on the instructions that we have covered so far.
  • Discuss simple algorithms for subtract,  decrement, etc.
  • If time: quick look at the LC-3 Assembler and Simulator
See Solution to LC-3 Program 1: (Handout #24)
Handout  #22, 23, and

Appendix A3 (for ADD, AND, NOT, LD, LEA, ST, BRcc, and TRAP).


   

3/2
L20
Handout #24: Solution to LC-3 Program 1
Handout #25: Flow of Control Slides (4 on 1pg)
Homework 4 partA
Discuss:
LC-3 ISA and "flow of control":
  • Review LC-3 Assembly Language
  • implementing HLL conditionals: example IF-ELSE
  • implementing HLL iteration: example WHILE
  • Requires two types of instructions:  conditional branch instructions (BRn, BRnz, ...) and unconditional branch (such BRnzp or BR )
Mystery Question #3: Due Monday March 5th:  Which three UTCS faculty are building the next generation computer?  And why - what problem are they solving? SEARCH in the CS Dept Web Pages or explore their research. Write your answer in 25-50 words and hand it in on Monday 3/5 Lecture 21 (for .5%). Note: I will accept anything reasonable.
Appendix A3:
BRcc

TRAP 5.4.6
HW4  
8
3/5
L21
Handout #26:  Array Slides part1 (4 on 1pg)
Paper copy of: Homework4 PartB
Discuss: Implementing HLL concepts:
  • Everyone wrote the LC-3 code for an if-(then)-else statement:
  • how to initalize a register to zero or non-zero
  • Thinking about "arrays and memory layout"
Solution to LC-3 Program 2
Appendix A3 for LDR and STR instruction     

3/7
L22
Handout #27: Array Slides part2 (4 on 1pg)
Discuss: Arrays
  • Memory Layout in Java
  • Programming with arrays (sequential access)
Notes on Arrays, including LC-3 Program 3, Memory Layouts, and a short discussion on 2D arrays.
LDR/STR
pg104, 5.3.3

Array Examples
5.4.2 - 5.4.4, figure 5.16, 7.2.3
   

3/8
D8
Handout #28: Solutions to Exam1 (not online)
Discuss: Programming with 1D Arrays
Notes:  LC-3 Program 4

 

3/9
L23
Handout #29: Assembler Slides (4 on 1pg)
Discuss: The Assembler
Assemblers
Notes on Assemblers
7.3
  HW4

3/12-
3/16

Spring Break - half way!

   
9
3/19
L24
Handout #30: 'Structure/Record' Slides (4 on 1pg)
Discuss: Arrays and Structures

Review:  Assemblers and Arrays

NEW:
Programming with arrays (random access)
Record/Structures (accessing data members of an object)
Notes (1st half on Structure Memory Layout)

 
 

3/21
L25
Handout: First 4 pages of Hmwk5 Question1
Discuss:
Wrapup Structures.
Reading/writing multi-byte Quantities:  Every ISA needs a unique load instruction for each multi-byte size supported in the ISA.
Notes (2nd half on Programming Structures)

Mystery Question #4:   Due Friday March 23rd.
Who is John Backus?  What invention is he well-known for?  Read about him (e.g. in the NYTimes).  What is his attitude toward school and work.  (Hint: ACM Turing Lecture is a good source as well.)  Write your answer in 25-50 words and hand it in on Friday 3/23  (for .5%). Note: I will accept anything reasonable.
 Handout #17 (Section 4.3)


 

3/22
D9
Discuss:
  • Hmwk5 Question 1:  Assemble a small program (for Pass1)
  • Structures: 
    • Working with non-zero offsets; 
    • structures that include an array or object
    • arrays of structures
    • Use real-world ISAs for multi-byte quantitites
  • Notes on the above topics.

   

3/23
L26
Handout #31: Function Call Supplement
Handout #32: Solutions to Hw4Q1,Q4,Q6 (not online, outside my office).  Back of the handout:  For FUN story by Dijkstra on Recursion.
Handout #33: Function slides Part 1 (4on1pg)
Hard copy of: Hmwk 5Q2 Assignment
Discuss: "Function Calls" aka "Method Calls"
What NEW instructions do we need? and Why?
What values must be stores (somewhere) per function call???
new instructions for "invoking a method"
Appendix A.3 for JSR, RET, and JMP instructions.

pp 5.4.5, 228-232


 HW5 Q2  
10
3/26
L27
Handout #34: Function slides Part 2 (4on1pg)

Discuss:
  • MQ4: Backus & looking at a Fortran example of do-while and if statement, and Bachus' focus on creating a compiler that could efficiently generate the assembly lang.  Also, Dijkstra's story on Recursion
  • Review JSR and JMP <register>  (RET is a pseudo instruction for JMP R7)
SIDEBAR:  What is the difference between the following 2 unconditional branch instructions:
BRnzp ENDIF and JMP R7  ???

Class discussion about compile-time, asm-time (pass1 and pass2), (and link time & load time), and of course run-time.  

a) The BRnzp is always naming the same location, and if the compiler uses .ORIG addr, then the address of  ENDIF could be known at compile time (but real world compilers don't choose the address).  

b) The JMP instruction will always have a value in the register that was stored at run-time.
  • Reviewing where to store the "function state": in registers (if possible);  in memory at a static location, such as the Fortran strategy;  and the (3rd) strategy is dynamic location of memory  by storing the state on the run-time stack.  
  • Sidebar:  When local variables are included with the run-time stack, then memory for local variables are allocated ONLY when the function is called.
  • Introduction to the Run-time stack and the concept of a "stack-frame" aka "activation record".

stacks:
P/P 10.1
Supplement #31
   

3/28
L28
Worksheet for in-class discussion, based on Function Supplement #31 (Page 5 and 6)
Discuss:
  • Concepts such as passing arguments by value or by address
  • Saving Registers - who saves them and why?  caller? or callee?
  • Two Common Strategies of Compiler Templates for Function Calls: 
    •  Using Registers when possible
    • CS310 Complete Stack Frame
Mystery Question #5: Due Friday March 30th.   COMPARE the CS310 Complete Stack Frame to the generic Stack Frame found in Handout #0 on page 3.  Write your answer in 25-50 words and hand it in on Friday  (for .5%). Note: I will accept anything reasonable.
stack frame
P/P: 14.3, and Supplement #31.
HW6  

3/29
D10
Discuss:
  • Work with the Compiler Template for Function Calls:  using a stack frame that includes args, return value, and local variables (along with other state): we're calling it the Complete Stack Frame.
Notes: Example using the CS310 complete stack frame
 Supplement #31    

3/30
L29
Handout #35: Solutions to Hmwk 5 Q2 (not online, outside TAY 4.136)
Discuss: Wrap-up Function Calls by writing the code together in class for a CS310 Complete Stack Frame. Here's the Solution.
Supplement #31
Notes from Disc10
   
11
4/2
L30

Handout #36: 
Addressing Mode Slides (4 on 1pg)
Discuss:  Addressing Modes (not on Exam2)







LC3 initial Addr Modes:
 
P/P5.3
focus on various "addressing modes"  for loads and stores.

PC relative
P/P 5.4: focus on BR/JSR

register indirect JMP, JSRR...

   

4/4
L31
Handout #37: Preparing for Exam 2 
Handout #38: Sample Reference Sheet for Exam2
Discuss:  Addressing Modes:
  • PC-relative:  assembly time vs run-time
  • What if the PC-relative offset field isn't sufficient?  How can we work around it?
  • Do addressing modes impact you?  Try writing code using the indirect register addressing mode?   the indexed addressing mode?
  • Here's the link to current RISC ISAs and Embedded ISAs, then click on Online Appendix C.  Browse pages 2&3, Read pages 4&5 about their addressing modes.  Have fun exploring a specific RISC ISA if you have an interest.
Notes on PC-relative Addressing Mode (and the Absolute Addressing Mode)

Handout #36


PC-relative Addr Mode
LD, ST, BR, LEA, JSR

Memory Indirect Addressing Modes: LDI/STI


   

4/5
D11
Discuss: Exam 2 Practice
  • Review the Function Call template focusing on Registers
  • Practice with Supplement #17: ISA Operand Taxonomy
    • Each ISA has 0..3 explicit operands (the others are implicit) and either memory or register operands.
    • ***Accumulator ISA (1 explicit operand for ADD)
    • ***"Stack Operand" ISA (0 explicit operands for ADD)
    • Three explicit operands for ADD: e.g. the LOAD-STORE ISA (with 3 register operands), and CISC ISA's such as the VAX who would have any combination of memory and register operands.
    • ***"Two explicit Operands" for ADD: e.g. the Intel ISA with at most one memory operand.
  • For any instruction: encode it (given the necessary facts); what is the size of the instruction; how many memory accesses were needed to fetch and execute the instruction.
  • Practice with the usage of LEA and LD to distinguish between them.
  • Sample Exam2 Problems
     

4/6
L32
Handout #39: Sample Exam2 Problems
Discuss:  What does a compiler symbol table would look like besides symbol name and value???

Study Quiz 2 (focusing on Arrays and Assemblers)
Notes on Compiler Symbol Table plus...

Local variables
12.5
 
   
12
4/9
L33
Handout #40: Solution to Hmwk 6 (partial)
Handout #41: Bit Manipulation Supplement
Last Minute Questions on Exam
Discuss: Where is your Data? Local Variables, Heap, Global Variables...
Notes on Compiler Symbol Table plus Introduction to Global Data, and Memory Layout:  Code, Global Data, Heap, and Runtime Stack
Whole program layout:
12.5, 19.4
   

4/9
Ex2
Exam 2, WEL 3.502, 7-9+




4/11
L34
Handout #42: Addressing Mode Supplement (not online)
(Handout #43) Hmwk 7 Question 1:  Recursive Call
Discuss: Bit Manipulation Motivation and Algorithms
Mystery Question #6: Due Friday 13th in class. Read Handout#0.  What are the 4 basic types of prevention techniques for exploits on the stack buffer overflow.  Which type do you think is most effective?  Write 25-50 words.  
Bit Manipultion
Handout #41,
P/P 2.6, 2.7.2
HW7
Q1
 

4/12
D12
Addressing Modes
Bit Manipulation
Notes: Bit Manipulation and Addressing Modes
Handout #42
Handout #41

 

4/13
L35
(Handout #44: HW7Q2)
Handout #45:
In-Class Worksheet (A sample stack frame with a local array, and P/P figure 12.7)
Handout #46:  Buffer Overflow Attack Slides (4 on 1pg)
Discuss: Stack Buffer Overflow
Stack Buffer Overflow and Preventions
Handout #0
 HW7
 
13
4/16
L36
Handout #47: I/O Part 1 Slides (4 on 1pg)
HW7Q3
Input/Output Micro-architecture
Input/Output MicroArchitecture
P/P 8.1
HW7 Q3  

4/18
L37
News: Exam2 returned today
Handout #48: Traps: Slides (4 on 1pg)
Discuss: Input/Output
Memory-mapped I/O
"Ports"
Programming: Polling using an input example: the keyboard.

Discuss: Traps (briefly)
Input/Output Polling
P/P 8.1-8.3


Traps
9.1
   

4/19
D13
Handout #49: Solutions to Exam2 (not online)
Discuss:
Input/Output:  
Focus on an Output  example using a modem.
Write a polling routine
How the trap instruction works
Writing a trap function
Notes
8.1-8.3, 9.1   

4/20
L38
Handout #50: Mystery Question 7:  Turn in on Monday
Discuss:
Motivation for Traps
Motivation for Interrupts
Notes on Motivation for Traps

Interrupt Motivation

P/P p211


  HW7
14
4/23
L39
Handout #51: Interrupt ISA/Micro-architecture Slides (4 on 1pg)
Hmwk8Q1: Java bit manipulation program
Discuss:
Interrupt Micro-architecture
Interrupt MicroArchitecture
P/P 8.5, 10.2
HW8  

4/25
L40
Handout #52: Interrupt Motivation and Software Architecture (not online)
Handout #53: Interrupt Architecture Supplement
Discuss:
Programming: Device Drivers for Interrupts

Interrupt Software and MicroArchitecture
Handout #53
   

4/26
D14
Discuss:
Interrupts:
  • Interrupt Hardware, focusing on the interrupt phase and the RTI:  Good practice in 10.2.3
  • Interrupt Software:  Good practice to read Pg7 of the Interrupt Supplement, and Slides for Hdt52.

   

4/27
L41
Handout #54: Linking Part1 Slides (4 on 1pg)
Also: Overview of the TRIPS Architecture (my paper copy emphasized pgs 44,46-49, including Figure 1 and 2)
Discuss:
Questions on Hmwk7,8, and all other topics
Interrupt Software Code
Linking/Loading Introduction
Mystery Question 8: Unveiling the UT-Austin TRIPS Processor: An Architecture for Scaling to the End of Silicon.  What does "Edge" stand for and why are they building the TRIPS Processor?  Write your answer in 25-50 words and hand it in on Monday in class  (for .5%). Note: I will accept anything reasonable.
Interrupt Software
Handout #53

Linking/Loading
P/P 7.4
   
15
4/30
L42
Handout #55: Linking/Loading Supplement
Handout #56: Linking/Loading Part2 Slides (4 on 1pg)
Handout #57: Exam3 Description
Handout #58: Partial Solutions to HW7 (not online)
Discuss: Linking Pass1, Pass2
Linking
P/P 9.2.5,

Linking
Supplement
   

5/2
L43
Study Quiz 3
Discuss:
Linking Libraries, including the concept of Dynamic Linked Libraries; Loading
    HW8

5/3
D15
Handout #59: Partial Solutions to Hmwk 8 Q2/Q5/Q6
Discuss:
Linking/Loading Worksheet, and other Questions.
TA Evaluations
     

5/4
L44
Mystery Question 9: Which key concepts did you particularly enjoy, or have impact, or want to explore more on your own???
Discuss: Exam 3 Review
If time: Threads, Context Switching, JVM, Intel ISA
CLASS Evaluation
     

5/4
EX3
Exam 3, 7-9p.m. WEL 3.502