CS352 Computer System Architecture: Spring 2002
(extras of handouts are outside my office TAY 4.136)
Course Agenda
Date
Lec #
Topic 
Reading BEFORE this date 
Out
In
01/14
1
Discuss:Introduction
Motivation for course;
Handouts #1: Course Logistics
#2: Course Topics
     
01/16
2
Discuss:  Basic performance concepts.
Handout #3: Partial slides
Chapter 1,  2-2.3     
01/18
3
Discuss: How to influence changes in CPI, IC, and CCT.  Amdahl's Law.  Benchmarks that you have encountered.
Handout #4: Hmwk 1
Chapter 2   HW 1  
01/23
4
Discuss: Benchmarking: which programs to use; how to measure; how to combine multiple measurements into 1 summary.  ISA design intro.
Handout #5: Partial benchmark slides
Chapter 2    
01/24   HW 1 due, 23:59 p.m. via email.     HW1
01/25
5
Discuss: ISA-I: ISA vs implementation; state; an ISA view of memory.
Handout #6: Hmwk 2 - due Wed 30th.
Chapter 3
 HW 2
 
01/28
6
Discuss: ISA-II:  Operands, History of Register Organization.
Handout #7, #8:  partial slides for ISA #1 and #2.
Chapter 3    
01/30
7
Discuss: ISA-III: Finish stack organization; 
Handout #9: ISA #3
     
02/01
8
Discuss: ISA-IV Addressing modes; Branch addressing; Strategies for implementing conditional branches; Encoding.    
HW2
02/04
9
Discuss: Encoding; Intel x86, Risc/Cisc; Compilers & ISA 
Handout #10: Reference for hmwk3; #12: Homework 3 part1; #13: Slides for lecture 10; #14: Compiler reading.
Appx B and Ch4.1-4.4 if needed.
 HW3p1
 
02/06
10
Discuss: Finish compilers; Datapath1:  ALU design with a bit of EE316 review. Intricacies of SUB, SLT. Handout #11: Background reading on the Java Virtual Machine (more detail than you really need for hmwk3), Handout #15: Homework 3 part2. Hdt #14,
Pp 230-240; 
 HW3p2
 
02/08
11
No class in exchange for night exam1    
 
02/11
 12
Discuss: Datapath 2: clock, register file, multi-clock cycle datapath with a shared bus
Handout #16: Solution to hmwk 2.  #17: slides for today's lecture.  News: Hmwk3 was extended 24hrs.
 Ch. 5.1-5.4 (focus on 5.4)  
HW3 p1 & p2
02/13
 13
Discuss: Datapath & Control; shared bus
 Hdt17 datapath
 
 
02/15
 14
Discuss: Control for a datapath (hardwired logic vs microcode)
Handout #18: Sample exam questions, #19: Exam1 Objectives, #20 Hmwk 3 solutions (required reading --- outside my office TAY 4.136 after Fri 5:30p.m.) #21 Partial slides for current lecture; Graded hmwk2's returned.
 Hdt17 datapath, 
5.4 control, 5.5 control
 
 
02/18
 15
Discuss: Quick look at what's different about the datapaths in 5.3/5.4.
Graded hmwk3's returned.
 5.3-5.4
 
 
02/20  16 Review for Exam1      
02/21   Night Exam1, 8-10 p.m. (WCH 1.120)      
02/22
 17
Guest Lecture given by Dr. Burger. He will be talking about his architecture research here at UT. The lecture is "required", and will be in our regular class room.   
 
 
02/25
 18
Discuss: Wrapup Ch5 (except 5.6); Pipelining Introduction (motivation, example pipeline, GANTT charts).  Handout #22: Slides for today. 6.1(thru pg 442)-6.2  
 
02/27
 19
Discuss: Pipelining: focus on data hazards
Handout #23 Homework 4 and 2 yellow worksheets to be used in Hmwk4. #24: Partial slides for today's lecture.
6.4-6.5
 H4
 
03/01
20
Discuss: Pipelining Hazards (finish data hazards; discuss implementing the control logic for data hazard stalling and register forwarding) 6.3-6.5    
03/04
 21
Discuss: Control Hazards: impact of branch penalty.  Handout #25: Control hazard slides #1-16.  Returned Exam 1.  See grades for the distribution. 6.6    
03/06
 22
Discuss: Control Hazards: branch prediction. Handout #26: Exam1 Solutions. 6.6.
 
 H4
03/08
 23
Discuss: Yes, we will have class today.  Answers to your questions, and 1bit/2bit dynamic prediction. pp498-502.
 
 
    Spring Break!      
03/18
 24
Discuss:  Finish advanced control hazards.  Handout #27: Slides for today (#17-24).  #28: Homework 5. Hdt27
 H5
 
03/20
 25
Discuss: Advanced pipelining (Instruction level parallelism; branch predication)
Handout #30: Solutions to Hmwk4.  #29: Slides (partial).
Ch 6.8    
03/22
 26
Discuss: Advanced pipelining 2 (compiler: loop unrolling; multi-issue)
Handout #31: Slides (partial) #32/33: superscalar definitions and examples.
Ch6.9; all of Ch6.
 
 
03/25
 27
Discuss: Finish advanced pipelining.  Handout #34: Front: Hmwk6; Back: Gantt chart example. #35: Reading on IA-64. Read Hdts 31-33.
 H6
 H5
03/27
 28
Discuss: Memory hierarchy motivation, issues, terminology. 
Handout #36:  For fun only (few details on current processor's pipelines and caches).  #37: Slides (partial).
 Back page of Hdt 34, and Hdt 35.
Ch7.1
 
 
03/29
 29
Governor's office cancelled our class (certainly surprised me!).
Handout: #38: Exam2 objectives (now online, and outside my office.). #39: Hmwk 5 solutions (Yes, #39 is outside my office now.) #40: Few exam2 problems (yes, #40 is outside my office now).
     
04/01
 30
Discuss:  basics; placement and identification issues --- i.e. mapping, and replacement.
Handout #41: Hmwk 6 solutions.
 Ch 7.1-7.3
 
 H6
04/03 31 Answer exam2 questions.      
04/04   Mid-Term, 8-10 p.m., WCH 1.120.      
04/05
32
No CS352 class today. Please read 7.1-7.3 for Monday.  
 
 
04/08
33
Discuss: Cache basics review; Write design issues; begin improving cache performance.  Handout: #42: Project handout #1.  #43: Slides. #44: Slides. Read 7.1-7.3, and 7.5
 Project (hdt#1)
 
04/10
34
Discuss: Improving cache performance (strategies impact miss rates,miss penalty, hit time). Handout #45 Slides (partial).      
04/12
 35
Discuss:  Accessing main memory via the bus. Handout #46 Slides (partial).
 Ch 7.4
   
04/15
 36
Discuss: Virtual Memory Basics; Handout #47 Slides (partial).
 Chapter 7
   
04/17
 37
Discuss: Virtual Memory & TLBs
Handout #49: partial slides; Handout #48: Project (hdt#2) online.
     
04/19
 38
Discuss: Finish TLBs.  Memory Hierarchy all together. Handout #50: Exam2 solutions.  #51: VM & cache slides. #52: Combining all the elements of the Memory Hierarchy: VM, TLB, and caches
 VM slides
 
 
04/22
 39
Discuss: Memory hierarchy (putting together VM, TLB, and caches).  Discuss flowchart.  Practice how they relate to each other by (1)Invalidating ('flush') cache blocks when writing out a dirty page to Mem.  and (2) Analyzing all  combinations of hits/misses for VM, TLB, cache.
 Hdt 52, Ch7
   
04/24
 40
Discuss: I/O: Busses: intro, synchronization, arbitration between bus masters.  Handout #53: Bus Slides.
 8.4
   
04/26
 41
Discuss: I/O: Busses: finish arbitration. Improving bus throughput: splitting a bus transaction into 2 transactions, pipelining arbitration and the split transactions.  Handout #54: Extra Credit Hmwk 7. #55/56: Supplements for bus lecture.
 8.4
Extra credit Hmwk7
 
04/29
 42
Discuss: I/O: Bus block transfers; RAID.  Handout #57: RAID slides. Handout #58: FYI only, not part of the final (DMA I/O and the memory hierarchy)
pg680-684, 692, Hdt #57, pg709.
   
05/01
 43
Discuss: Finished RAID (large reads/writes vs small reads/writes). Parallel Architectures Overview. Handout #59, 60 (focus on 60): Partial slides.
 Chapter 9 --- skip 719-726, 731-732, 9.6(NEW as of 5/5)
  Proj
5/2
05/03
 44
Wrapup. Handout #61: Final Exam Objectives. Handout #62: Solutions to Hmwk 7 (the extra credit homework) are only available outside TAY 4.136. NOTE: For those of you who didn't attempt this Hmwk, I suggest that you use Hmwk7 as your memory hierarchy practice problems. I suggest that you do NOT read these solutions until you have taken Hmwk 7 as an "exam".) NEW 5/5: I have editted Handout #61 to shorten the reading of Chapter 9.  
 Hmwk7
05/11   Final - you can take it at either time.      
05/14   Final 2 - you can take it at either time.