The parts of the user interface are laid out giving a certain amount of screen to each unit. There are two additional sections of the screen, one for user input and one for general simulator status.
The Integer Unit, Branch Unit, and Floating Point Unit screen portions display the status of their pipelines. An "S" is displayed to indicate stalled and an "E" to indicate executing. The instructions that are currently being executed are displayed next to the stage they are utilizing. The BPU unit also displays the contents of the condition register, link register, and count register.
The Instruction Queue displays the valid instructions in the queue during each cycle and the number of instructions dispatched.
The Memory Hierarchy displays: CARB, CACC, Memory, ISB and FPSB. The CARB (Cache Arbitration)stage displays the unit that is arbitrating for cache access. The CACC (Cache Access) displays which unit has current access to the cache. If there is no current activity involving the cache, these stages display "idle". The Memory Unit displays the unit that it is servicing in the current cycle or "idle" is no memory access is needed. The ISB (Integer Store Buffer) and FPSB (Floating Point Store Buffer) displays the current instruction stored in the respective buffers.
An option to the screen is the GPR and FPU register display. By toggling "f" for float or i for integer, the simulator will display the list of FPR's or GPR's and their values.
A helpful feature for debugging is the ppc601.out output file. The following inputs allows items to be dumped to this file for examination.