Cache storage is implemented as a two dimensional array of Nblocks by Nlines. Sectors are replaced by a Least Recently Used (LRU) strategy. The cache unit can handle one access per cycle. Cache requests are handled by priority with fpu stores being the highest, integer stores next and instruction fetches lowest.
The floating point store buffer (fpsb) and the integer store buffer (isb)
are used to buffer an instruction when the cache is busy with another unit.
When cache access is needed by the floating point unit or the integer unit and the cache is not available,
the address is held in the one element buffers until it achieves access.