Design Overview

This simulator was designed and coded to follow the PPC601 microprocessor in terms of its functional units, and the actions that each performs. For more information on the PowerPc Microprocessor, see the Background Information web page.

PPC601 Simulator Functional Units:

The simulator clock cycle is broken into four phases, "start", "do", "end", and "report statistics". The report statistics phase is a book keeping phase, and not part of the chip design, only the simulator. If the simulator is in the normal state (user input n), the member function sim-step is called. This function initiates the four phases for each of the units.

The first phase is the "start stage". In a start phase a unit will gather all of its current state information and make any external function calls to pass information to other units. For the most part, no work for this clock cycle i s done in a start phase, however if an instruction is in the branch unit, the target address is calculated.

The "do stage" is where the majority of work is done. At this point the module may make changes that would make the state information unstable if read now. All necessary calculations and decoding are done in this phase.

In the "end stage" the new state information is written, and any clean up that is necessary is done such as collaspsing queues or updating registers.

The "report status stage" updates the collection entities with information from this phase, such as stalls, instruction types and if a unit retries an instruction. In this phase, the simulator sends results to the UIO to update the graphical interface.

For those interested, there is an informative abstract by Chris Edmonson-Yurkanan on "Why you should build a Superscalar Pipeline Simulator".


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Last modified: Thu Sep 12 13:35:35 CDT