MIPS Instruction Set architecture  Fall 97
		  REFERENCE SYNTAX CARD (EXAM #2 Subset)
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This "load/store" architecture has 32 general purpose registers named R0...R31, 
two multiply/divide registers named Hi and Lo, and does NOT have a condition 
code register(CCR), R0 is actually the constant 0.  Note: R0 is not 
modified if it is ever used as a destination operand.  We will not use R1.  

The machine code for each of the following instructions is one word; 
memory is byte addressable; a word = 4bytes, and words must be 
word-aligned; halfwords must be half-word aligned; no alignment restrictions 
on bytes.  Although real MIPS chips are configurable to be either little or 
big endian, memory is LITTLE ENDIAN on the UT PCSPIM!!!!!
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	# precedes comments, and $ for register
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 LB/LH/LW $d, addressing_mode
 SB/SH/SW $s, addressing_mode # 2nd operand is the destination
^LA       $d, addressing_mode
^LI  $d, n16                   
 LUI $d, n16                  # $d = logical left shift of n16 by 16bits
------------------------------------------------------------------
 ADD   $d, $s1, $s2    
 ADDI  $d, $d1, n16  
 SUB   $d, $s1, $s2	# s1 - s2
^MUL   $d,$s1,$s2/n16   
^DIV   $d,$s1,$s2   
 AND   $d, $s1, $s2    
 ANDI  $d, $d1, n16 
 OR    $d, $s1, $s2    
 ORI   $d, $d1, n16  
 XOR   $d, $s1, $s2    
 XORI  $d, $d1, n16 
^ROL   $d, $s1, $s2     # $d = rotate left $s1 by the amount $s2
^ROR   $d, $s1, $s2     # $d = rotate right $s1 by the amount $s2
 SLLV  $d, $s1, $s2     #$d = logical shift left $s1 by the 
 SLL   $d, $s1, n5            	# amount $s2/n5 (zero fill)
 SRLV  $d, $s1, $s2     #$d = logical shift right $s1 by the 
 SRL   $d, $s1, n5 		# amount $s2/n5 (zero fill) 
------------------------------------------------------------------
 SLT   $d, $s1, $s2    
 SLTI  $d, $s1, n16
------------------------------------------------------------------
 J     label 
 JR    $d
 JAL   label  
^B     label  
 BEQ   $s1, $s2, label
 BNE   $s1, $s2, label
 BGEZ  $s1, label 
 BGTZ  $s1, label
 BLEZ  $s1, label
 BLTZ  $s1, label
^BEQZ  $s1, label 
^BNEZ  $s1, label
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ASSEMBLER DIRECTIVES
	.data	
	.text  
label:  .space    n
label: 	.byte	n1, n2, ...
label: 	.half   n1, n2, ...
label: 	.word   n1, n2, ...
	sym = value		 
	.align  n # align the next location in this segment to an address 
			#divisible by 2 ^ n ( ie n is exponent of 2 )
------------------------------------------------------------------
STACK MANIPULATION INSTRUCTIONS
^PUSHW $s 
^POPW  $d
------------------------------------------------------------------
^MOVE    $d, $s 
^NEG     $d, $s 
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LEGEND: the / indicates an option (select one of the itemized choices)
	addressing_mode: addr  OR   displacement($n)
	addr: a symbolic_name, decimal value, or 0x followed by hexadec. value
	d, s, s1, and s2: values in the range of 0..31
	label: a symbolic_name
	n16 will be sign extended, at runtime, to a 32bit value
	n16, n32 may be: decimal digits; "0x followed by hex digits";
	    'character';  or a symbolic name (assembler uses value in SymTable)
	n5: a 5bit unsigned integer; symbolic name, assembler uses val in S.T.