Changkyu Kim

Changkyu Kim

Publications || Experience || Education || Presentations || Contact Information

Research Scientist of Throughput Computing Lab, Intel Coporation
Email: changkyu.kim (at) i n t e l . c o m

Research

I am currently a research scientist at the Throughput Computing Lab at Intel Labs, Santa Clara, CA. Before joining Intel Labs, I completed my PhD. in Computer Science from the University of Texas at Austin. I received a M.S and a B.S from Seoul National University in Computer Engineering.

Throughput Computing is a major priority for my research interest. One of my most significant research focus in this area is: analysis and synergistic combination of emerging applications including visual computing (graphics, physical simulation), database/data-mining, AI, real-time analytics, with upcoming architecture trends, such as multi/many-core, reconfigurable, GPU, heterogeneous computing.

In the past, I worked on the

NUCA (Non-Uniform access Cache Architecture), the TRIPS, and the TFlex project under Dr. Doug Burger and Dr. Steve Keckler.

Publications

Sort vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs (VLDB, 2009) (coming soon)

ClearPath: Highly Parallel Collision Avoidance for Multi-Agent Simulation (ACM SCA, 2009)

Multitasking Workload Scheduling on Flexible-Core Chip Multiprocessors (PACT, 2008)

Atomic Vector Operations on Chip Multiprocessors (ISCA, 2008)

Second Life and the New Generation of Virtual Worlds (IEEE Computer, 2008)

Composable Lightweight Processors (MICRO, 2007)

On-Chip Interconnection Networks of the TRIPS Chip (IEEE Micro, 2007)

A NUCA Substrate for Flexible CMP Cache Sharing (IEEE TPDS, 2007)

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor (MICRO, 2006)

Implementation and Evaluation of On-Chip Network Architectures (ICCD, 2006)

A NUCA Substrate for Flexible CMP Cache Sharing (ICS, 2005)

Scaling to the End of Silicon with EDGE Architectures (IEEE Computer, 2004)

TRIPS: A Polymorphous Architecture for Exploiting ILP, TLP, and DLP (ACM TACO, 2003)

NUCA: A Non-Uniform Cache Access Architecture for Wire-Delay Dominated On-Chip Caches (IEEE Micro Top Picks, 2003)

Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture (IEEE Micro Top Picks, 2003)

Exploiting ILP, DLP, and TLP Using Polymorphism in the TRIPS Architecture (ISCA, 2003)

An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches (ASPLOS, 2002)

Professional Experience

Throughput Computing Lab, Intel Corporation
- Research Scientist (06/2007 ~ Present)

University of Texas at Austin
- Research Assistant (06/2001 - 05/2007)
- Teaching Assistant (08/2000 - 05/2001)

LG-CIT (LG Corporate Institute of Technology)
- Research Engineer (01/1999 ~ 03/2000)

RIACT (Research Institute Of Advanced Computer Technology), Seoul National University
- Research Assistant (03/1997 ~ 02/1999)

Education

Ph.D. in Computer Sciences at The University of Texas at Austin, U.S.A., May 2007.
M.S. in Engineering at Department of Computer Engineering, Seoul National University, Korea, Feb 1999.
B.S. in Engineering at Department of Computer Engineering, Seoul National University, Korea, Feb 1997.

Invited and Conference Presentations

VLDB, Lyon, France, Aug, 2009

MICRO, Orlando, FL, Dec, 2007

Samsung Electronics, Seoul, Korea, Jul, 2007

Seoul National University, Seoul, Korea, Jul, 2007

KAIST (Korea Advanced Institute of Science and Technology), Daejeon, Korea, Jul, 2007

Korea University, Seoul, Korea, Jul, 2007

HPCA, Austin, TX, Feb, 2006

ISCA, Madison, WI, Jun, 2005

Intel, Shrewsbury, MA, Jan, 2003

HP/Compaq, Marlboro, MA, Jan, 2003

Samsung Electornics, Seoul, Korea, Dec, 2002

ASPLOS, San Jose, CA, Oct, 2002

IBM, Austin, TX, Jan, 2002

Contact Information

Intel Corporation
Microprocessor and Programming Research
3600 Juliette Ln SC12-303
Santa Clara, CA, 95054
Email: changkyu.kim (at) i n t e l . c o m