Publications by type
[Conference papers]
[Journal papers]
[Book chapters]
[Workshop papers]
[Miscellaneous papers]
[Technical reports]
Note: all documents are also available in Postscript; replace the "pdf" extension with "ps" on any link
Conference papers
- "Scalable
Selective Re-execution for EDGE Architectures," R. Desikan, S. Sethumadhavan,
D.C. Burger, and S.W. Keckler
11th International Conference on Architectural Support for Programming Languages
and Operating Systems (ASPLOS), October, 2004.
- "Coherence
Decoupling: Making Use of Incoherence," J.Huh, J. Chang, D.C. Burger,
and G.S. Sohi
11th International Conference on Architectural Support for Programming Languages
and Operating Systems (ASPLOS), October, 2004
- "Static
Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures,"
R. Nagarajan, S. Kushwa, D.C. Burger, K.S. McKinley,
C. Lin, and S.W. Keckler
2004 International Conference on Parallel Architectures and Compilation Techniques
(PACT), September, 2004.
- "Scalable
Hardware Memory Disambiguation for High ILP Processors," L. Sethumadhavan,
R. Desikan, D.C. Burger, C.R. Moore, and S.W. Keckler
36th International Symposium on Microarchitecture (MICRO), December, 2003.
- "Universal
Mechanisms for Data-Parallel Architectures," K. Sankaralingam, S.W. Keckler,
W. Mark, and D.C. Burger
36th International Symposium on Microarchitecture (MICRO), December, 2003.
- "Designing
Ultra-Large Instruction Issue Windows," D.C. Burger
invited paper to the 2003 Asia-Pacific Computer System Architecture Conference
(ACSAC), September 2003
- "Routed
Inter-ALU Networks for ILP Scalability and Performance," K. Sankaralingam,
V. Singh, S.W. Keckler, and D.C. Burger
International Conference on Computer Design (ICCD), pp. 170-177, October,
2003.
- "Exploiting
Microarchitectural Redundancy For Defect Tolerance," P. Shivakumar,
S.W. Keckler, C.R. Moore, and D.C. Burger
International Conference on Computer Design (ICCD), pp. 481-488, October,
2003
- "Exploiting
ILP, TLP, and DLP with the Polymorphous TRIPS Architecture," K. Sankaralingam,
R. Nagarajan, H. Liu, C. Kim, J. Huh,
D.C. Burger, S.W. Keckler, and C.R.
Moore
2003 International Symposium on Computer Architecture (ISCA), June, 2003.
- "Guided
Region Prefetching: A Cooperative Hardware/Software Approach," Z. Wang,
D.C. Burger, S.K. Reinhardt, K.S. McKinley, and C.W. Weems.
2003 International Symposium on Computer Architecture (ISCA), June, 2003.
- "Microprocessor
Pipeline Energy Analysis," H. Hanson, R. Nagarajan, S.W. Keckler,
C.R. Moore, and D.C. Burger
IEEE International Symposium on Low Power Electronics and Design (ISLPED),
August, 2003.
- "A Wire-Delay
Scalable Microprocessor Architecture for High Performance Systems,"
S.W. Keckler, D.C. Burger, C.R. Moore, R. Nagarajan, K. Sankaralingam, V.
Agarwal, M.S. Hrishikesh, N. Ranganathan, and P. Shivakumar.
2003 International Solid-State Circuits Conference (ISSCC), February, 2003.
- "An Adaptive,
Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches,"
C.K. Kim, D.C. Burger, and S.W. Keckler.
International Conference on Architectural Support for Programming Languages
and Operating Systems (ASPLOS-X), October, 2002.
- " Modeling
the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
,"
P. Sivakumar, M. Kistler, S.W. Keckler, D.C. Burger, and L. Alvisi.
International Conference on Dependable Systems and Networks (DSN),
June, 2002.
- " The Optimal
Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays,"
M.S. Hrishikesh, K. Farkas, N.P. Jouppi, D.C. Burger, S.W. Keckler, and P.
Sivakumar.
29th International Symposium on Computer Architecture (ISCA),
May, 2002.
- "A Design
Space Evaluation of Grid Processor Architectures,"
R. Nagarajan, K. Sankaralingam, D.C. Burger, and S.W. Keckler.
34th International Symposium on Microarchitecture (MICRO), December,
2001.
- "Exploring
the Design Space of Future CMPs,"
J. Huh, D.C. Burger, and S.W. Keckler.
International Conference on Parallel Architectures and Compilation Techniques
(PACT), September, 2001.
- "Filtering
Superfluous Prefetches Using Density Vectors,"
W.F. Lin, S.K. Reinhardt, D.C. Burger, and T.R. Puzak.
International Conference on Computer Design (ICCD), September,
2001.
- "Static
Energy Reduction Techniques for Microprocessor Caches,"
H. Hanson, V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D.C. Burger.
International Conference on Computer Design (ICCD), September,
2001.
- "A Neuroevolution
Method for Dynamic Resource Allocation on a Chip Multiprocessor,"
F.J. Gomez, D.C. Burger, and R. Miikkulainen.
International Joint Conference on Neural Networks (IJCNN), July,
2001.
- "Measuring
Experimental Error in Microprocessor Simulation,"
R. Desikan, D.C. Burger, and S.W. Keckler.
28th International Symposium on Computer Architecture (ISCA),
pp. 266-277, July, 2001.
- "Reducing
DRAM Latencies with a Highly Integrated Memory Hierarchy Design,"
W.F. Lin, S.K. Reinhardt, and D.C. Burger.
7th Symposium on High-Performance Computer Architecture (HPCA),
pp. 301-312, January, 2001.
- "Clock Rate
versus IPC: the End of the Road for Conventional Microarchitectures,"
V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D.C. Burger.
27th International Symposium on Computer Architecture (ISCA),
June, 2000.
- "DataScalar
Architectures,"
D.C. Burger, S. Kaxiras, and J.R. Goodman.
24th International Symposium on Computer Architecture (ISCA),
pp. 338-349, June, 1997.
- "Efficient
Synchronization: Let Them Eat QOLB,"
A. Kägi, D.C. Burger, and J.R. Goodman.
24th International Symposium on Computer Architecture (ISCA),
pp. 170-180, June, 1997.
- "Exploiting
Optical Interconnects toEliminate
Serial Bottlenecks,"
D.C. Burger and J.R. Goodman.
3rd International Conference on Massively Parallel Processing Using
Optical Interconnects (MPPOI), October, 1996
- "Memory
Bandwidth Limitations of Future Microprocessors,"
D.C. Burger, J.R. Goodman, and A. Kägi.
23rd International Symposium on Computer Architecture (ISCA),
pp. 78-89, May, 1996.
- "Techniques
for Reducing Overheads of Shared-Memory Multiprocessing,"
A. Kägi, N. Aboulenein, D.C. Burger, and J.R. Goodman.
9th International Conference on Supercomputing (ICS), July, 1995.
- "Accuracy
vs. Performance in Parallel Simulation of Interconnection Networks,"
D.C. Burger and D.A. Wood.
9th International Parallel Processing Symposium (IPPS), April,
1995.
- "Paging
Tradeoffs in Distributed Shared-Memory Multiprocessors,"
D.C. Burger, R.S. Hyder, B.P. Miller, and D.A. Wood.
Supercomputing `94, November, 1994.
- "Exploration
Geophysics-An Interactive Approach,"
H.R. Burger and D.C. Burger.
Geological Society of America, Abstracts with programs, 21,
p. A369, 1989.
Journal articles
- "Static Energy Reduction Techniques for Microprocessor
Caches,"
H. Hanson, M.S. Hrishikesh, V. Agarwal, S.W. Keckler, and D.C. Burger.
IEEE Transactions of VLSI, 2002.
- "Bottlenecks in Multimedia
Processing with SIMD-Style Extensions and Architectural Enhancements,"
D. Talla, L.K. John, and D.C. Burger.
IEEE Transactions on Computers, 2002.
- "Designing a Modern Memory Hierarchy with Hardware Prefetching,"
W.F. Lin, S.K. Reinhardt, and D.C. Burger.
IEEE Transactions on Computers special issue on memory systems, 50 (11), November, 2001.
- "Limited Bandwidth to Affect Processor Design,"
D.C. Burger, J.R. Goodman, and A. Kägi.
IEEE Micro, special issue on advanced
memory architectures, 17 (6), November/December 1997.
- "Changing Interaction of Compiler and Architecture,"
S. Adve, D.C. Burger, R. Eigenmann, A. Rawsthorne, M.D. Smith,
C. Gebotys, M. Kandemir, D.J. Lilja, A. Choudhary, J. Fang, and P. Yew,
IEEE Computer, 30 (12), pp. 51-56, December, 1997.
- "Guest Editors' Introduction: Billion-Transistor Architectures,"
D.C. Burger and J.R. Goodman.
IEEE Computer, 30
(9), pp. 46-48, September, 1997.
- "Memory Systems,"
D.C. Burger.
ACM Computing Surveys, 28 (1), pp. 63-65, March, 1996.
- "Paging Tradeoffs in Distributed Shared-Memory Multiprocessors,"
D.C. Burger, R.S. Hyder, B.P. Miller, and D.A. Wood.
The Journal of Supercomputing, 10 (1), pp. 87-104, 1996.
Book chapters
- "A Technology-Scalable Architecture for Fast Clocks and High ILP,"
K. Sankaralingam, R. Nagarajan, D.C. Burger, and S.W. Keckler.
Interaction Between Compilers and Computer Architectures," edited by
G. Lee and P. Yew, pp. 117-139, Kluwer Academic Publishers, 2001.
- "
Hardware Techniques to Improve the Performance of the Processor/Memory Interface,"
D.C. Burger.
Ph.D. Dissertation, Computer Sciences Department, University of Wisconsin-Madison, December, 1998.
- "Memory Systems,"
D.C. Burger, J.R. Goodman, and G.S. Sohi.
The Handbook of Computer Science and Engineering, CRC Press, 1997.
Also appears in The Handbook of Electrical Engineering, CRC Press, 1997.
- Software to accompany Exploration
Geophysics of the Shallow Subsurface,
D.C. Burger and H.R. Burger.
Prentice-Hall, Inc., 1992.
Workshop papers
- "A Characterization of Speech Recognition on Modern Computer Systems,"
K. Agaram, S.W. Keckler, D.C. Burger.
4th IEEE Workshop on Workload Characterization, at MICRO-34, December, 2001.
- "A Technology-Scalable Architecture for Fast Clocks and High ILP,"
K. Sankaralingam, R. Nagarajan, D.C. Burger, S.W. Keckler.
5th Workshop on the Interaction of Compilers and Computer Architecture, at HPCA-7, January, 2001.
- "Maximizing Performance/Area Implementations for Future Single-Chip Servers,"
J. Huh, D.C. Burger, and S.W. Keckler.
IBM Austin Center for Advanced Studies Workshop, January, 2001.
- "Characterizing the SPHINX Speech Recognition System,"
K. Agaram, S.W. Keckler, and D.C. Burger.
IBM Austin Center for Advanced Studies Workshop, January, 2001.
- "Why Future Architectures will be Memory-Centric,"
D.C. Burger and J.R. Goodman.
Innovative Architecture for Future Generation High_Performance Processors and Systems, IEEE Computer Society Press, p. 92, 1998.
- "System-Level Implications of Processor/Memory Integration,"
D.C. Burger.
Workshop on Mixing Logic and DRAM, at ISCA-24, June, 1997.
- "Simulation of the SCI Transport Layer
on the Wisconsin Wind Tunnel,"
D.C. Burger and J.R. Goodman.
2nd International Workshop on SCI-based High-Performance Low-Cost Computing, pp. 57-66, March, 1995.
Newsletters/Opinion
- "The SimpleScalar
Tool Set, Version 2.0,"
D.C. Burger and T.M. Austin.
Computer Architecture News, 25 (3), pp. 13-25,
June, 1997.
- "A World-Wide Computer Architecture
Home Page,"
M.D. Hill and D.C. Burger.
Computer Architecture News, 23 (3), June, 1995.
Technical Reports
- "Combining Hyperblocks and Exit Prediction to Increase Front-End
Bandwidth and Performance,"
N. Ranganathan, R. Nagarajan, D.C. Burger, and S.W. Keckler.
UT-Austin Computer Sciences Technical Report TR-02-41, September, 2002.
- "On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories,"
R. Desikan, S.W. Keckler, and D.C. Burger.
UT-Austin Computer Sciences Technical Report TR-02-47, September, 2002.
- "Modeling the Impact of Device and Pipeline Scaling on the Soft Error Rate of Processor Elements,"
P. Shivakumar, M. Kistler, S.W. Keckler, D.C. Burger, and L. Alvisi.
UT-Austin Computer Sciences Technical Report TR-02-19, April, 2002.
- "An Adaptive Cache Structure for Future High-Performance Systems.,"
C. Kim, D.C. Burger, and S.W. Keckler.
UT-Austin Computer Sciences Technical Report TR-02-10. February, 2002.
- "Assessment of MRAM Technology Characteristics and Architectures,"
R. Desikan, S.W. Keckler, and D.C. Burger.
UT-Austin Computer Sciences Technical Report TR-01-36, October, 2001.
- "Sim-alpha: a Validated, Execution-Driven Alpha 21264 Simulator,"
R. Desikan, D.C. Burger, S.W. Keckler, and T.M. Austin.
UT-Austin Computer Sciences Technical Report TR-01-23, October, 2001.
- "Impact of Technology Scaling on Instruction Execution Throughput,"
M.S. Hrishikesh, D.C. Burger, and S.W. Keckler.
UT-Austin Computer Sciences Technical Report TR-00-06, June, 2001.
- "Static Energy Reduction Techniques in Microprocessor Caches,"
H. Hanson, S.W. Keckler, and D.C. Burger.
UT-Austin Computer Sciences Technical Report TR-01-18, June, 2001.
- "The Effect of Technology Scaling on Microarchitectural Structures,"
V. Agarwal, S.W. Keckler, and D.C. Burger.
UT-Austin Computer Sciences Technical Report TR-00-02, May, 2001.
- "Characterizing the SPHINX Speech Recognition System,"
K. Agaram, S.W. Keckler, D.C. Burger.
UT-Austin Computer Sciences Technical Report TR-00-33. January, 2001.
- "Technology Independent Area and Delay Estimates for Microprocessor Building Blocks,"
S. Gupta, S.W. Keckler, D.C. Burger.
UT-Austin Computer Sciences Technical Report TR-00-05. February, 2001.
- "SimpleScalar Simulation of the PowerPC Instruction Set Architecture,"
K. Sankaralingam, R. Nagarajan, S.W. Keckler, and D.C. Burger.
UT-Austin Computer Sciences Technical Report TR-00-04, February, 2001.
- "Memory Hierarchy Extensions to the SimpleScalar Tool Set,"
D.C. Burger, A. Kägi, M.S. Hrishikesh.
UT-Austin Computer Sciences Technical Report TR-99-25, September, 1999.
- "The SimpleScalar Tool Set, Version 2.0,"
D.C. Burger and T. M. Austin.
UW Computer Sciences Technical Report 1342, June, 1997.
- "
Evaluating Future Microprocessors: the SimpleScalar Tool Set,"
D.C. Burger, T.M. Austin, and S. Bennett.
University of Wisconsin-Madison Computer Sciences Technical Report 1308, July, 1996.
- "
Parallelizing Appbt for Shared-Memory Multiprocessors,"
D.C. Burger and S. Mehta.
University of Wisconsin-Madison Computer Sciences Technical Report 1286, September, 1995.
- "The Declining
Effectiveness of Dynamic Caching for General-Purpose Microprocessors,"
D.C. Burger, J.R. Goodman, and A. Kägi.
University of Wisconsin-Madison Computer Sciences Technical Rreport 1261, January, 1995.