CS352 Spring 2007 (#55015) Course Schedule

Date

Day

Lec #

Topic Administrivia, plus What is Computer Architecture"

Reading BEFORE this date 

Out

In
(Due)

Jan. 22

M

1

"Administrivia, plus What is Computer Architecture"? (ppt)

 

 

 

Jan. 24

W

2

Computer Elements (ppt)

P&H Chapter 1, P&H 2.1-2.4

HW#1

 

Jan. 29

M

3

ISA I - Basic instruction sets, arithmetic operations (ppt)

Handout #1

 

 

Jan. 31

W

4

ISA II - Memory/control instructions, MIPS, other ISAs

P&H 2.5-2.9


HW#1

Feb. 5

M

5

ISA II - Memory/control instructions, MIPS, other ISAs (ppt)


HW#2 

 

Feb. 7

W

6

ISA III - CISC vs. RISC, instruction set design

Handout #2

 

 

Feb. 12

M

7

ISA IV - Compilation and Assembly (ppt)

P&H 2.10-2.18, A.1-A.5, A.9



Feb. 14

W

8

Microarchitecture I - Computer arithmetic (ppt)

P&H 3.1-3.5

 

 

Feb. 15






HW#2

Feb. 19

M

9

Microarchitecture II - Datapath elements (ppt)

P&H 3.9, Chapter 5

 


Feb. 21

W

10

Microarchitecture III - Basic pipelining (ppt)

P&H Chapter 6.1-6.2 

 

 

Feb. 26

M

11

 Exam review

 

 HW#3

 

Feb. 28

W

Exam #1



 

 

Mar. 5

M

12

Microarchitecture IV - Pipeline implementation (ppt)

P&H 6.4-6.7

 

 HW#3

(1-7)

Mar. 7

W

13

Microarchitecture V - Data and control hazards, bypassing (ppt)

P&H Chapter 4


 HW#3

(8)

Mar. 19

M

14

Memory I - Introduction to caching and memory hierarchies (ppt)

P&H 7.1-7.2, Critical_Path Paper

 

 

Mar. 21

W

15

Memory II - Improving cache performance (ppt)

P&H 7.3

 


Mar. 26

M

16

Memory III - More on Caches

Handout #3


 

Mar. 28

W

17

Memory IV - Cache design and non-uniform caches (ppt)

 

 HW#4

 

Apr. 2

M

18

Memory V - Virtual memory, page tables, and DRAM design (ppt)

P&H 7.4

 


Apr. 4

W

19

Memory VI - Virtual memory and TLBs (ppt)

P&H 7.5-7.12

 

 

Apr. 9

M

20

ILP I - Multiple-issue cores (ppt)

P&H 6.8

 

 HW#4

Apr. 11

W

21

 ILP II - VLIW architectures (ppt)

 P&H 6.9

 

 

Apr. 16

M

Exam #2



 

 

Apr. 18

W

22

ILP III - Superscalar microarchitectures (ppt)

P&H 6.10-6.12

Project

Starter Help

 

Apr. 23

M

23

ILP IV - Prediction and speculation (ppt)

P&H 6.6

 

 

Apr. 25

W

24

ILP V - Case study in modern processor design

Handout #4,Alpha21264, two_level_branch_prediction,

 

 

Apr. 30

M

25

Systems I - Multiprocessor design and programming models

P&H 9.1-9.5

 

 

May 2

W

26

Systems II - Cache coherence

Handout #5

 

 

May 4





 

 Project

May 10


 

 

 

 

Project extension

May 14

M

Final exam

Time: 2:00-5:00 pm

 

 

 

HW#4 and HW#5 schedule will be posted soon.