Date	Day	Lecture	Topic	Readings	Assigned	Due
Aug. 31	TH	1	Overview: Computer Architecture and Technology Trends	-
Sep. 5	T	2	Performance Evaluation and Intro to ISA Design	H&P: Chapter 1 #1: Moore: Cramming More Components #2: Emer and Clark: VAX Characterization
Sep. 7	TH	3	ISA Design	H&P: Chapter 2 #3: Patterson and Ditzel: The Case for RISC #4: Colwell et al.: Instruction Sets and Beyond...	HW#1
Sep. 12	T	4	Cache Memories	H&P: Chap 5.1 - 5.7 #5: Hill: Case for Direct Mapped Caches
Sep. 14	TH	5	Memory Hierarchies and DRAM	H&P: Chapter 5.8 - 5.18 #6: Jouppi: Victim Buffers		HW#1
Sep. 19	T	6	Pipelining I	H&P: Appendix A #7: Kunkel and Smith: Optimal Pipelining
Sep. 21	TH	7	Pipelining II	#8: Borch et al.: Loose Loops Sink Chips	HW#2
Sep. 26	T	8	Instruction-level Parallelism I Static Scheduling	H&P: Chapter 4 #9: Rau and Fisher: Instruction Level Parallel Processing
Sep. 28	TH	9	Instruction-level Parallelism II: Front-end Design	H&P: Chapter 3.1 - 3.5 #10:Yeh and Patt: Two Level Adaptive Branch Prediction
Oct. 3	T	10	Instruction-level Parallelism III: Register Renaming	H&P: Chapter 3.6 - 3.10
Oct. 5	TH	11	Instruction-level Parallelism IV: Dynamic Scheduling	H&P: Chapter 3.11 - 3.15
Oct. 10	T	12	Instruction-level Parallelism V: Aggressive Speculation	#11: Fields et al.: Critical Path Analysis		HW #2
Oct. 12	TH	13	Alpha 21264 Case Study	-
Oct. 17	T	--	Exam I
Oct. 19	TH	14	Multiprocessors I: Shared Memory and Message Passing	H&P: Chapter 6.1-6.7
Oct. 24	T	15	Multiprocessors II: Coherence Protocols (Guest Lecture: Steve Keckler)	#14: Lenoski et al.: Stanford DASH
Oct. 26	TH	16	Coherence Protocols (Contd.)	H&P: Appendix I #15: Li and Hudak: Coherence in Shared Memory
Oct 31	T	17	Multiprocessors III: Consistency Models	#16: Adve and Gharacharloo: Consistency Tutorial	HW #3
Nov 2	TH		Multiprocessors IV: Interconnection Networks	H&P: Chapter 8 #25: Scalar Operand Networks
Nov. 7	T	19	Research I: Speculative Threads	#17: Sohi et al.: MultiScalar Processors #18: Stefan et al.: A Scalable Approach to TLS
Nov. 9	TH	20	Research II: Transactional Memory	#19: Herlihy and Moss: Transactional Memory		HW #3
Nov. 14	T	21	Case Study I: TRIPS	#20: Burger et al.: Scaling to End of Silicon with the EDGE ISA
Nov. 16	TH	22	Case Study II: TRIPS	#21: Sankaralingam et al.: Design and Implementation of TRIPS
Nov 21	T	23	Great Debates II: VLIW vs Superscalar	#12: McNairy and Soltis: Itanium 2 Processor #13: Tendler et al.: Power 4 System
Nov 23	TH		Thanksgiving (No class)
Nov. 28	T	24	Great debates III: Shared Memory vs. Message Passing vs. Transactions	#22: Hammond et al.: The Stanford Hydra CMP #23: Moore et al.: Log Transactional Memory #24: MPI homepage
Nov. 30	TH	-	Exam 2
Dec 5	T	-	Project Presentation 1
Dec. 7	TH	-	Project Presentation 2