Week	Date	Reading	Presenter
1	1/18	Class Organization
2	1/25	The IBM System/360 Model 91: Machine Philosophy and Instruction Handling (supplement) HPS, A New Microarchitecture: Introduction and Rationale (supplement)	Mark Gebhart Boris Grot
3	2/1	Parallel Operation in the Control Data 6600 Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors Kroft,	Kevin Bush Paul Gratz
4	2/8	A Preliminary Architecture for a Basic Data-Flow Processor Executing a Program on the MIT Tagged-Token Dataflow Architecture WaveScalar	Min Kyu Jeong Hadi Esmaeilzadeh
5	2/15	Instruction Sets and Beyond: Computers, Complexity, and Controversy MIPS: A Microprocessor Architecture The 801 Minicomputer The Case for the Reduced Instruction Set Computer	Guhan Ravi Tom Hartin
6	2/22	Architecture and Applications of the Connection Machine, Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities, Cost-Effective Parallel Computing, Amdahl's Law in the Multicore Era	Renee St. Amant Jyotsna Verma
7	3/21	The Cedar System and an Initial Performance Study CEDAR: A Large-Scale Multiprocessor The NYU Ultracomputer - Designing a MIMD, Shared-Memory Parallel Machine The NYU Ultracomputer - Designing an [sic] MIMD Shared Memory Parallel Computer	Behnam Robatmili Dong Li
8	3/28	Architecture and Applications of the HEP Multiprocessor Computer System Simultaneous Multithreading: Maximizing On-Chip Parallelism Performance Analysis of k-ary n-cube Interconnection Networks Performance of the Cray T3E Multiprocessor	Bhuvana Ramachandran Joel Hestness
9	4/4	A New Solution to Coherence Problems in Multicache Systems Using Cache Memory to Reduce Processor-Memory Traffic The Stanford DASH Multiprocessor The Scalable Coherence Interface (SCI) Further reading: Distributed Directory Scheme: Scalable Coherence Interface	Sadia Sharif Jyotsna Verma
10	4/11	DDM - A Cache-Only Memory Architecture Memory Coherence in Shared Virtual Memory Systems Tempest and Typhoon: User-Level Shared Memory	Tom Hartin Behnam Robatmili
11	4/18	One-Level Storage System Slave Memories and Dynamic Storage Allocation Structural Aspects of the System/360 Model 85, Part II: The Cache	Mark Gebhart Kevin Bush
12	4/25	Cache Memories Sequential Program Prefetching in Memory Hierarchies Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers Cache Write Policies and Performance	Renee St. Amant Guhan Ravi
13	5/2	How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs "Weak Ordering - A New Definition" "Does SC + ILP = RC?"	Bhuvana Ramachandran Min Kyu Jeong
14	5/9	EV8: The Post-Ultimate Alpha (Slides) Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor Algorithms for scalable synchronization on shared-memory multiprocessors Efficient synchronization primitives for large-scale cache-coherent multiprocessors	Boris Grot Joel Hestness