I. Control signal example Let's look at the RTL for ADD and figure out how the control signals should be set. RTL Control signal settings --- ----------------------- 1) MAR <- PC, PC<-PC+1 GatePC, LD.MAR, PCMX=PC+1, LD.PC 2) MDR <- MEM[MAR] MIO.EN, LD.MDR, R.W=RD 3) IR <- MDR GateMDR, LD.IR 4) DECODE -- 4) GPR[IR[11:9]] <- SR1MX=8.6, DRMX=11.9, SR2MX=SR2OUT, GPR[IR[8:6]] + GPR[IR[2:0]] ALUK=ADD, GateALU, LD.REG setCC() LD.CC II. LC-3 Control logic state diagram - see Figure C.2 on p. 568 in P&P - Shows all possible possible RTL steps and how they are connected - Note that for all instructions, the first four steps are identical, and after the 4th step, we know exactly what kind of instruction it is. This means that we can start to think about a "program" that can be used to execute the sequence of microinstructions from different macro instructions. For example: while(1){ 1) MAR <- PC, PC <- PC+1 2) MDR <- MEM[MAR] 3) IR <- MDR 4) BEN <- IR[11]&N + IR[10]&P + IR[9]&Z /* decode */ if(IR[15:12]==0001) { /* ADD Rx, Rx, Rx */ 5) GPR[IR[11:9]] <- GPR[IR[8:6]] + (IR[5] ? SEXT(IR[4:0]) : GPR[IR[2:0]]), set(CC) } else if(IR[15:12]==0010) { /* LD imm */ 5) MAR <- PC[15:9] + SEXT(IR[8:0]) 6) MDR <- MEM[MAR] 7) GPR[IR[11:9]] <- MDR, set(CC) } ... and so on for the rest of the instructions ... } Special notes: - "Int" arc leading away from state 18 to state 49 - this is for interrupts; we will handle these later - "R" signal indicates that the memory is "ready" - if you are accessing the memory and ~R, then you have to stay and wait in that state - "BEN" = branch enable - which holds the result of testing the condition code registers III. Partitioning the LC-3 design (see figure C.1 in appendix) - Design components - Control logic - generates control signals for datapath (39 bits) - receives info from datapath (7 bits) - receives info from external devices and memory (2 bits) - implements state machine - Datapath - receives control signals - executes each step of an instruction according to control signals - exchanges info with memory, I/O - Memory, I/O - receives two control signals (R.W and MIO.EN) - generates additional local control signals - interacts with datapath IV. How can we actually implement the control logic state machine? - Two strategies - Hardwired - direct combinational logic for all next states and outputs (similar to our vending machine example) - Hardwired control - Output signals - a function of the current state and inputs (maybe) - Example: GatePC = 1 iff in one of following states: 1, 21, 31, 33 - Next state - also a function of current state and inputs - if state==1, next state is "2" - if state = 4 and IR[15:12]==0001, then next state = "6" - Microprogrammed - build a table in memory that encodes most/all of the next state and output information V. Microprogrammed control - Basic idea - We can write down all of the control signals we need in one long vector - Each state in our state machine diagram (Figure C.2) has a different vector - We can store these vectors in a table (special memory called the "microcode store") and just look them up (rather than computing the values using combinational logic) - The only other thing we need is a simple machine that looks up the vectors - Example vectors Gate Signals LD Signals MUX/MISC ---------------- ---------------------- ------------------------------- State MARMX PC ALU MDR PC REG CC IR MAR MDR BEN MARMX PC SR1 ALUK DR MIO.EN R.W --------------------------------------------------------------------------------- "18" 0 1 0 0 1 0 0 0 1 0 0 X PC+1 X X X 0 1 "33" 0 0 0 0 0 0 0 0 0 1 0 X X X X X 1 1 "35" 0 0 0 1 0 0 0 1 0 0 0 X X X X X 0 1 "32" 0 0 0 0 0 0 0 0 0 0 1 X X X X X 0 1 "1" 0 0 1 0 0 1 1 0 0 0 0 X x 8:6 ADD 11:9 0 1 The five vectors shown above covers the 5 steps of the ADD instruction (according to our state diagram in Figure C.2) - A couple of notes: - We set R.W = 1 to read from memory at all times (except when we want to write it) - We have added another register: BEN (branch enable) that is not really a part of the datapath, but is used by the control logic - We have omitted the mux control signals for two special muxes - Select bits to route to register DR inputs (Figure C.6a) - Select bits to route to register SR1 inputs (Figure C.6b) - What about the SR2MUX? - we can hardwire IR[5] to this control signal! We are also missing something pretty substantial...how do we encode the next state? - We can encode also encode this in the control vector! - However - we have some special cases to allow branches in the state machine Below is the rest of the each vector describing each step: State (binary) J[5:0] COND[2:0] IRD /* possible next states */ ----------------------------------------- "18" 010010 100001 101 0 33, 49 "33" 100001 100011 001 0 35, 33 "35" 100011 100000 000 0 32 "32" 100000 000000 000 1 0-15 "1" 000001 010010 000 0 18 There is some moderately confusing logic in Table C.2, Figure C.5 Basic idea: - J field in vector holds next state encoding - COND field indicates special tests that must occur to compute the true next state - IRD says to ignore J and COND because you are in state 32 and want to use the bits from the IR to select the next state - The combination of these signals allows us to select the next state whenever we have a couple of possible choices COND table: COND[2:0] -------- unconditional (nothing special) 000 test for memory ready 001 test for branch taken 010 test for addressing mode on JSR/JSRR 011 test for privileged mode (on RTI) 100 test for interrupt (only in state 18) 101 Let's do another one - how about JSR State (binary) J[5:0] COND[2:0] IRD /* possible next states */ ----------------------------------------- "18" 010001 100001 101 0 33, 49 "33" 100001 100011 001 0 35, 33 "35" 100011 100000 000 0 32 "32" 100000 000000 000 1 0-15 "4" 000100 20, 21 "20" 010100 18 VI. State encoding - Why does all of this funky logic for next state selection work? - Because we have been very careful in assigning state encodings - This is also why the state encodings seem a bit weird - 6 bits are necessary since there are a total of ~54 states to encode