CS352H Fall 2009 Schedule, Handouts, and Reading

 
Week Date Lec # Topic Reading BEFORE this date  Additional Resources Out In
(Due)
1 8/27 L1 Introduction, What is Computer Architecture, Technology Trends   Moore paper Moore paper reading assignment - Critique due Tuesday 9/1/09  
2 9/1 D1,L2 Moore paper discussion
ISA I 		Moore paper, P&H Chapter 1, 2.1-2.6   HW #1 assigned - due Thursday 9/10/09 Moore paper critique due
2 9/3 L3 ISA II P&H Rest of Chapter 2, Appendix B for HW reference      
3 9/8 L4 ISA III - MIPS Integer ALU I RISC paper, P&H Chapter 3.1, 3.2, Appendix C.1-C.6 RISC paper RISC paper reading assignment - Critique due Tuesday 9/15/09  
3 9/10 L5 MIPS Integer ALU II P&H Chapter 3.3, 3.4   HW #2 assigned - due Thursday 9/17/09 HW #1 due
4 9/15 D2 RISC paper discussion
More MIPS Integer ALU II 		Complexity paper Complexity paper Complexity paper reading assignment - Critique due Tuesday 9/22/09 RISC paper critique due
4 9/17 L6 MIPS Floating Point P&H Rest of Chapter 3   HW #3 assigned - due Thursday 10/1/09 HW #2 due
5 9/22 L7 Complexity paper discussion
Performance Measurement 		P&H Chapter 4.1-4.5     Complexity paper critique due
5 9/24 L8 MIPS Processor Organization P&H Chapter 4.1-4.5, Appendix C.4 (on CD)   HW #4 assigned - due Thursday 10/8/09  
6 9/29 L9 MIPS Pipeline P&H Rest of Chapter 4      
6 10/1 L10 MIPS Pipeline - Hazards P&H Rest of Chapter 4   HW #5 assigned - due Thursday 10/15/09
Verilog template file (rcAdder.v) for 16-bit adder
Testbed file (tb_rcAdder.v) for 16-bit adder 		HW #3 due
7 10/6 L11 MIPS Instruction Level Parallelism (ILP) P&H Rest of Chapter 4      
7 10/8 L12 MIPS ILP II P&H Rest of Chapter 4     HW #4 due
8 10/13 L13 Memory Hierarchies - Caches P&H Chapter 5.1-5.3, 5.7, 5.9   Project (incl HW #6) assigned - due Thursday 10/29/09
LC3.5 Unpipelined 		 
8 10/15 L14 Caches II P&H Rest of Chapter 5     HW #5 due
9 10/20 M1 Midterm Exam Coverage - P&H Chapters 1-4 and parts of appendices B and C assigned above Old CS310 midterm for question style reference
Old midterm not mine, though 		   
9 10/22 L15 Multilevel and Coherent Caches P&H Rest of Chapter 5      
10 10/27 L16 Virtual Memory and Virtual Machines P&H Rest of Chapter 5      
10 10/29 L17 Virtual Memory and Virtual Machines II P&H Rest of Chapter 5     HW #6 due
11 11/3 L18 I/O Systems P&H Chapter 6      
11 11/5 Equipment failure - walk I/O Systems P&H Chapter 6      
12 11/10 L19 I/O Systems P&H Chapter 6      
12 11/12 L20 Multicore, Multiprocessors - I P&H Chapter 7.1-7.6   HW #7 assigned - due Thursday 12/3/09  
13 11/17 L21 Multicore, Multiprocessors - II P&H Rest of Chapter 7      
13 11/19 L22 Multicore, Multiprocessors - III P&H Chapter 7      
14 11/24 L23 GPU Architecture P&H Appendix A      
14 11/26 TG Thanksgiving Break        
15 12/1 L24 GPU Architecture II P&H Appendix A      
15 12/3 L25 Review, Discussion       HW #7 and Project due

Material and slides adapted from Computer Organization and Design, Patterson & Hennessy.
Slides and assignments adapted from Prof. Mary Jane Irwin at Penn State, Prof. Steve Keckler at UT, and Dr. Haran Boral at UT.

Last modified: 01/21/10 Don Fussell, fussell@cs.utexas.edu