/*******************************
* File Name: tb_rcAdder.v
* Author: Dong Li  DongLi@CS.Utexas.edu
* Date: 9/22/2009
* Description: the test bench for 
* the ripple-carry adder
*
*Please notice, This is a simple
*test bench, Only 3 operations are enabled
*Only result is checked. 
*You are responsible to add more inputs to 
*test your design, and check all the results
********************************/
`timescale 100ps / 100ps 
//note: each time unit is 100ps now
//for example, #10 means 1ns

module testbench();

// Inputs of rcADDER
reg CLK;
reg RESET;
reg [1:0]  OPERATION;
reg [15:0] OPERAND0, OPERAND1;

// Output of rcADDER
wire [15:0] RESULT ;
wire CARRYOUT, OVERFLOW, READY;

//CLK generation (100Mhz, period = 50*100ps*2 = 10ns)
always #50 CLK   = ~CLK; 

//declare the adder module
rcAdder adder1(
	.CLK(CLK),
	.RESET(RESET),
	.OPERATION(OPERATION),
	.OPERAND0(OPERAND0),
	.OPERAND1(OPERAND1),
	.RESULT(RESULT),
	.CARRYOUT(CARRYOUT),
	.OVERFLOW(OVERFLOW),
	.READY(READY)
    );


    // Initialize Inputs
    initial begin
	$display("time,RESET, OPERAND1[15:0], OPERATION[1:0], OPERAND0[15:0], RESULT[15:0], CARRYOUT, OVERFLOW, READY \n");

	//initial the input
	CLK = 0;
	RESET = 0;
	OPERAND0=16'b0000_0000_0000_0000;
	OPERAND1=16'b0000_0000_0000_0000;
	OPERATION=2'b00;

	//reset the system
	#110    
	RESET = #1'b1;
	#200
	RESET = #1'b0;
	#100;

	//send input to the module
	
	@(posedge CLK);#10;   //this line means, wait until next CLK posedge, then, wait another 10 time units, which is 1ns in total     
	OPERAND0=16'b0000_0000_0000_0001;
	OPERAND1=16'b0000_0000_0000_0010;
	OPERATION=2'b01;

	@(posedge CLK);#10;        
	OPERAND0=16'b0000_0000_0000_1001;
	OPERAND1=16'b0000_0000_0001_1110;
	OPERATION=2'b10;

	@(posedge CLK);#10;        
	OPERAND0=16'b0000_0000_0000_0000;
	OPERAND1=16'b0000_0000_0000_0000;
	OPERATION=2'b00;

	@(posedge CLK);#10;        
	OPERAND0=16'b0000_1010_1000_0000;
	OPERAND1=16'b0000_0100_0100_0001;
	OPERATION=2'b01;

	@(posedge CLK);#10;        
	OPERAND0=16'b0000_0000_0000_0000;
	OPERAND1=16'b0000_0000_0000_0000;
	OPERATION=2'b00;


	
        //the first output is expected here, so, check the results here. 
	//Please notice, Here only result is checked. During grading, 
	//I will test all the output signal
	@(posedge CLK);
	if(RESULT != 16'b0000_0000_0000_0011) begin
	    $display ("ERROR @ %5d \n", $time);
	    $finish;
	end

	@(posedge CLK);        
	if(RESULT != 16'b0000_0000_0001_0101) begin
	    $display ("ERROR @ %5d \n", $time);
	    $finish;
	end

	@(posedge CLK);        
	if(RESULT != 16'b0000_0000_0000_0000) begin
	    $display ("ERROR @ %5d \n", $time);
	    $finish;
	end

	@(posedge CLK);        
	if(RESULT != 16'b0000_1110_1100_0001) begin
	    $display ("ERROR @ %5d \n", $time);
	    $finish;
	end

	@(posedge CLK);        
	if(RESULT != 16'b0000_0000_0000_0000) begin
	    $display ("ERROR @ %5d \n", $time);
	    $finish;
	end

	#100
	$display("All tests completed successfully\n\n");

	$finish;
    end


    always @ ( posedge CLK) begin
	$display("%5d	%b	%5d	%2b	%5d	%5d	%b	%b	%b\n", $time,RESET, OPERAND1[15:0], OPERATION[1:0], OPERAND0[15:0], RESULT[15:0], CARRYOUT, OVERFLOW, READY );
    end

    endmodule