• DVS bibliography at Friedrich-Alexander University Erlangen-Nuremberg>


• Power bib (bibtex format) at Friedrich-Alexander University Erlangen-Nuremberg >





• Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, and Doug Burger. Clock rate versus ipc: The end of the road for conventional microarchitectures. In Proceedings of the 27th Annual International Symposium on Computer Architecture, June 2000.

• Vikas Agarwal, Stephen W. Keckler, and Doug Burger. Scaling of microarchitectural structures in future process technologies. Technical Report TR2000-02, Department of Computer Sciences, The University of Texas at Austin, Austin, TX, February 2000.

• Anant Agarwal. Raw computation. Scientific American, 1999.

• David H. Albonesi. Dynamic ipc/clock rate optimization. In Proceedings of the 25th Annual International Symposium on Computer Architecture, pages 282-292, Barcelona, Spain, June 1998.

• David H. Albonesi. The inherent energy efficiency of complexity-adaptive processors. In Power Driven Microarchitecture Workshop in Conjunction with ISCA98, volume 1998, June 1998.

• Bharadwaj S. Amrutur and Mark A. Horowitz. Speed and power scaling of srams. IEEE Journal of Solid-State Circuits, 35:175-185, 2000.

• Manish Anand, Edmund B. Nightingale, and Jason Flinn. Self-tuning wireless network power management. In 9th Annual International Conference on Mobile Computing and Networking (MOBICOM '03), pages 176-189, September 2003.

• T S Anantharaman and R Bisiani. A hardware accelerator for speech recognition algorithms. In Proceedings of the 13th International Symposium on Computer Architecture, pages 216-223, June 1986.

• C. Anderson, J. Petrovich, J. Keaty, and G. Nusbaum. Power4 physical design. In International Solid-State Circuits Conference, 2001.

• Jonathan Babb, Matthew Frank, and Anant Agarwal. Solving graph problems with dynamic computation structures. In SPIE Photonics East: Reconfigurable Technology for Rapid Product Development & Computing. Unknown, 1996.

• R. Iris Bahar, Gianluca Albera, and Silatha Manne. Power and performance tradeoffs using various caching stategies. In ISLPED98, pages 64-69, Monterey, CA, USA, 1998.

• R.S. Bajwa, N. Schumann, and H. Kojima. Power analysis of a 32-bit risc microcontroller integrated with a 16-bit dsp. In Proceedings of the 1997 international symposium on Low power electronics and design, pages 137-142. ACM, ACM, August 1997.

• Luiz Andre Barroso, Kourosh Gharacharloo, and Edouard Bugnion. Memory system characterization of commercial workloads. In Proceedings of the 27th International Symposium on Computer Architecture, 1998.

• Roland Bechade, Roy Flaker, Bruce Kauffmann, Steve Kenyon, Charles London, Steve Mahin, Kim Nguyen, Dac Pham, Alan Roberts Sebastian Ventrone, and Tim VonReyn. A 32b 66 mhz 1.8w microprocessor. In International Solid-State Circuits Conference, pages 208-209, 1994.

• Frank Bellosa. The benefits of event-driven energy accounting in power-sensitive systems.

• Frank Bellosa. The case for event-driven energy accounting. Technical Report TR-I4-01-07, Friedrich-Alexander-Universitat Erlangen-Nurnberg, 2001.

• Frank Bellosa. Temperature-aware microarchitecture: Extended discussion and results. Technical Report CS-2003-08, University of Virginia Department of Computer Science, 2003.

• Luca Benini and Giovanni De Micheli. System-level power optimization: Techniques and tools. In ACM Transactions on Design Automation of Electronic Systems, volume 5 of ACM Transactions on Design Automation of Electronic Systems, pages 115-192. ACM, April 2000.

• Mark Bohr. Directions and challenges in integrated circuit scaling. Lecture at UT-Austin, March 2000.

• Anita Borg, Wolfgang Blau, Wolfgang Graetsch, Ferdinand Herrmann, and Wolfgang Oberle. Fault tolerance under unix. ACM Transactions on Computer Systems, 7(1):1-24, 1989.

• Shekhar Borkar. Design challenges of technology scaling. IEEE Micro, 19(4):23-29, July-August 1999.

• David Brooks and Margaret Martonosi. Dynamic thermal management for high-performance microprocessors. In Proceedings of the 7th International Symposium on High-Performance Computer Architecture. HPCA, January 2001.

• David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual Symposium on Computer Architecture (ISCA), pages 83-94, 2000.

• David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In booktitle, June 2000.

• D.M. Brooks, P. Bose, S.E. Schuster, H. Jacobson, P.N. Kudva, A. Buyuktosunoglu, J. Wellman, V. Zyuban, M. Gupta, and P.W. Cook. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors. IEEE Micro, 20(6):26-44, November/December 2000.

• Doug Burger and Todd M. Austin. The simplescalar tool set version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin, June 1997.

• Douglas C. Burger, James R. Goodman, and Alain Kagi. The declining effectiveness of dynamic caching for general-purpose microprocessors. Technical Report TR2000-02, The University of Wisconsin-Madison, Department of Computer Science, January 1995.

• Doug Burger, James R Goodman, and Alain Kagi. Memory bandwidth limitations of future microprocessors. In Proceedings of the 23rd International Symposium on Computer Architecture, May 1996.

• Doug Burger, Stephanos Kaxiras, and James R Goodman. Datascalar architectures. In Proceedings of the 24th International Symposium on Computer Architecture, 1997.

• J. Adam Butts and Gurindar S. Sohi. A static power model for architects. In Proceedings of 33rd Annual International Symposium on Microarchitecture, December 2000.

• Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook, and David Albonesi. An adaptive issue queue for reduced power at high performance. In Workshop on Power-Aware Computers Systems, held in conjunction with ASPLOS, Nov 2000.

• Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook, and David Albonesi. An adaptive issue queue for reduced power at high performance. Lecture Notes in Computer Science, 2008:25, 2001.

• George Cai. Architectural level power/performance optimization and dynamic power estimation, 1999.

• NASA Ames Research Center. Nas parallel benchmarks. http://www.nas.nasa.gov/cgi-bin/software/start, 2001.

• Anantha Chandrakasan. Low power circuit and system design, 2000. International Electron Device Meeting short course.

• Naehyuck Chang, Kwanho Kim, and Hyung Gyu Lee. Cycle-accurate energy consumption measurement and analysis: Case study of arm7tdmi. In Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000., pages 185-190, 2000.

• Alan Jay Smith Charles H.Perleberg. Branch target buffer design and optimization. IEEE transactions on Computers, 42(4):396-412, 1993.

• Rita Yu Chen, Mary Jane Irwin, and Raminder S. Bajwa. An architectural level power estimator. In Power Driven Microarchitecture Workshop in conjunction with ISCA98, June 1998.

• Rita Yu Chen, Robert M. Ownes, and Mary Jane Irwin. Validation of an architectural level power analysis technique. In Proceedings of ACM/IEEE Design Automation Conference, pages 242-245. ACM/IEEE, June 1998.

• Compaq Computer Corporation. Alpha 21264 Microprocessor Hardware Reference Manual, July 1999.

• Compaq Computer Corporation. Compiler Writer's Guide for the Alpha 21264, 1999.

• Microsoft Corporation. Designing and optimizing microsoft windows ce 3.0 for real-time performance, June 1999.

• Harvey Cragon. Elements of Computer Architecture and Implementation, chapter 6, pages 287-316. Unknown, [edition edition, 2000.

• R. Das, M. Uysal, J. Saltz, and Yuan-Shin S. Hwang. Communication optimizations for irregular scientific computations on distributed memory architectures. Journal of Parallel and Distributed Computing, 22(3):462-478, 1994.

• Rajagopalan Desikan, Doug Burger, and Stephen W. Keckler. Measuring experimental error in microprocessor simulation. In Proceedings of the 28th Annual Symposium on Computer Architecture, pages 266-277, 2001.

• Keith Diefendorff. Power4 focuses on memory bandwidth. Microprocessor Report, 13(13), October 1999.

• Steven Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, and Eby G. Friedman. Energy aware design: Managing static leakage energy in microprocessor functional units. In Proceedings of the 35th annual ACM/IEEE International Symposium on Microarchitecutrejj, pages 321 -- 332, November 2002.

• Dan Ernst, Krisztian Flautner, Trevor Mudge, Nam Sung Kim, Sidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, DAvid Blaauw, and Todd Austin. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, pages 7 -- 18, December 2003.

• Federico Faggin, Marcian E. Hoff, Stanley Mazor, and Masatoshi Shima. The history of the 4004. IEEE Micro, 16(6):10-20, December 1996.

• Jeanne Ferrante, Karl J Ottenstein, and Joe D Warren. The program dependence graph and its use in optimization. ACM Transactions on Programming Languages and Systems, 9(3):319-349, July 1987.

• Kriztian Flautner and Trevor Mudge. Vertigo: Automatic performance-setting for linux. In OSDI2002, pages 105-116, 2001.

• Krisztián Flautner, Trevor Mudge, and Steve Reinhardt. Automatic performance setting for dynamic voltage scaling. In 7th Annual Int. Conf. Mobile Computing and Networking 2001, pages 260-271, 2001.

• K. Flautner, N. Kim, S. Martin, D. Blaauw, and T. Mudge. Drowsy caches: Simple techniques for reducing leakage power. International Symposium on Computer Architecture, pages 148 -- 157, June 2002.

• Michael J. Flynn, Patrick Hung, and Kevin W. Rudd. Deep-submicron microprocessor design issues. IEEE Micro, July 1999.

• Daniele Folegnani and Antonio Gonzalez. Energy-effective issue logic. In 28th International Symposium on Computer Architecture, pages 230-239, July 2001.

• International Technology Roadmap for Semiconductors. International technology roadmap for semiconductors, 1999 edition, 1999. SIA Roadmap.

• Stephen Forrest, Paul Burrows, and Mark Thompson. The dawn of organic electronics. IEEE Spectrum, 37(8):29-34, August 2000.

• Bruce A. Gieseke, Randy L. Allmon, Daniel W. Bailey, Bradley J. Benschneider, Sharon M. Britton, John D. Clouser, Harry R. Fair III, James A. Farrell, Michael K. Gowan, Christopher L. Houghton, James B. Keller, Thomas H. Lee, Daniel Leibholz, Susan C. Lowell, Mark D. Matson, Richard J. Matthew, Victor Peng, Michael D. Quinn, Donald A. Priore, Michael J. Smith, and Kathryn E. Wilcox. A 600 Mhz superscalar RISC microprocessor with out-of-order execution. In IEEE International Solid-State Circuits Conference, pages 176-177, 451, February 1997.

• Ricardo Gonzalez and Mark Horowitz. Energy dissipation in general purpose processors. In IEEE International Symposium on Low Power Electronics, pages 12-13, October 1995.

• Liam Goudge and Simon Segars. Thumb: reducing the cost of 32-bit risc performance in portable and consumer applications. In Proceedings of the 1996 COMPCON, pages 176-181, September 1996.

• M. Gowan, L. Biro, and D. Jackson. Power considerations in the design of the alpha 21264 microprocessor. In Proceedings of ACM/IEEE Design Automation Conference, pages 726-731. ACM/IEEE, June 1998.

• Linley Gwennap. Power issues may limit future cpus. editorial in Microprocessor Report, August 1996.

• Bill Hamburgen. Itsy: A platform for pocket computing research, April 1999.

• Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, and Doug Burger. Static energy reduction techniques for microprocessor caches. In Proceedings of the International Conference on Computer Design (ICCD), September 2001.

• Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, and Doug Burger. Static energy reduction techniques for microprocessor caches. IEEE Trans. Very Large Scale Integr. Syst., 11(3):303-313, 2003.

• Heather Hanson. Comparison of leakage energy reduction techniques. Technical Report TR-01-18, Computer Sciences Department, University of Texas at Austin, June 2001.

• Heather Hanson. Static power in microprocessor caches. Master's thesis, The University of Texas at Austin, May 2001.

• Eric Hao, Po-Yung Chang, Marius Evers, and Yale N. Patt. Increasing the instruction fetch rate via block-structured instruction set architectures. In IEEE Proceedings of the 29th Annual International symposium on Microarchitecture. IEEE, December 1996.

• Seongmoo Heo, Kenneth Barr, and Krste Asanovic. Temperature and power aware architectures: Reducing power density through activity migration. In Proceedings of the 2003 International Symposium onLow-power electronics and design", pages 217-222, 2003.

• Toshiro Hiramoto and Makoto Takamiya. Low power and low voltage MOSFETs with variable threshold voltage controlled by back-bias. IEICE Transactions on Electronics, E83-C(2):663-660, February 2000.

• Yoshinori Asahi Hisao Yoshimura and Fumitomo Matsuoka. Scaling scenario of multi-level interconnects for future cmos lsi. In Symposium on VLSI Technology Digest of Technical Papers, pages 143-144, 2001.

• Masatada Horiuchi. A new dynamic-threshold SOI device having an embedded resistor and a merged body-bias-control transistor. In Proceedings of the IEEE International Electron Devices Meeting, pages 419-22, December 1998.

• Mark Horowitz, Thomas Indermaur, and Ricardo Gonzalez. Low power digital design. In IEEE Symposium on Low Power Electronics, pages 8-11, 1994.

• Mark Horowitz, Ron Ho, and Ken Mai. The future of wires. In Semiconductor Research Corporation Workshop on Interconnects for Systems on a Chip, May 1999.

• Xuedong Huang, Fileno Alleva, Hsiao-Wuen Hon, Mei-Yuh Hwang, and Ronald Rosenfeld. The sphinx-ii speech recognition system: An overview. Technical report, School of Computer Science, Carnegie Melllon University, 1992.

• Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas. A framework for dynamic energy efficiency and temperature management. In 33rd International Symposium on Microarchitecture (MICRO), December 2000.

• K. Imai, K. Yamaguchi, H. Onishi, T. Kudo, A. Ono, K. Noda, Y. Goto, H. Fujii, M. Ikeda, K. Kazama, S. Maruyama, T. Kuwata, and T. Horiuchi. A 0.13-um cmos technology integrating high-speed and low-power/high-denisty devices with two different well/channel structes. In IEDM 99, pages 667-670. IEEE International Electron Devices Meetings, 1999.

• Pentium III processor for the sc242 at 450MHz to 1.13GHz. Intel Corporation, June 2000. Order Number 244452-008.

• International technology roadmap for semiconductors, 2000 update, overall technology roadmap characteristics, 2000. http://public.itrs.net/Files/2000UpdateFinal/ ORTC2000final.pdf.

• M. J. Irwin. Asic tutorial. 12th Annual IEEE ASIC/SoC Workshop Slides, Low Power Design for Systems on a Chip, September 1999.

• A. Iyer and D. Marculescu. Run-time scaling of microarchitecture resources in a processor for energy savings. In Cool Chips Workshop, held in conjunction with MICRO-33, 2000.

• A. Iyer and D. Marculescu. Power aware microarchitecture resource scaling, 2001.

• John Arends Jeff Scott, Lea Huang Lee and Bill Moyer. Designing the low-power mcore architecture. Workshop on Power Driven Microarchitecture, June 1998.

• T.E. Jeremiassen and S.J. Eggers. Static analysis of barrier synchronization in explicitly parallel programs. In International Conference on Parallel Architectures and Compilation Techniques, pages 171-180, August 1994.

• Daniel Jimenez, Heather Hanson, and Calvin Lin. Boolean formula-based branch prediction for future technologies. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, September 2001.

• Paolo Faraboschi Joseph A. Fisher and Giuseppe Desoli. Custom-fit processors: Letting applications define architectures. In Proceedings of the 29th annual IEEE/ACM international symposium on Microarchitecture, pages 324-335, Paris, France, December 1996.

• Russ Joseph and Margaret Martonosi. Run-time power estimation in high performance microprocessors. In Proceedings of International Symposium on Low Power Electronics and Design, pages 135-140, 2001.

• Milind B. Kamble and Kanad Ghose. Analytical energy dissipation models for low power caches. In ACM/IEEE International Symposium on Low-Power Electronics and Design, pages 143-148, 1997.

• Tejas Karkhanis, James E. Smith, and Pradip Bose. Saving energy with just in time instruction delivery. In Proceedings of the 2002 International Symposium on Low Power Electronics and Design, pages 178 -- 183, 2002.

• Stefanos Kaxiras, Zhigang Hu, Girija Narlikar, and Rae McLellan. Cache-line decay: A mechanism to reduce cache leakage power. In Workshop on Power Aware Computer Systems, 2000.

• Stefanos Kaxiras, Zhigang Hu, and Margaret Martonosi. Cache-line decay: Exploiting generational behavior to reduce leakage power. In The 28th Annual International Symposium on Computer Architecture, pages 240-251, July 2001.

• Kimberly Keeton, David A Patterson, Yong Quiang He, Roger C Raphael, and Walter E Baker. Performance characterization of a quad pentium pro smp using oltp workloads. In Proceedings of the 27th International Conference on Computer Architecture, 1998.

• R.E. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24-36, March/April 1999.

• R.E. Kessler. The alpha 21264 microprocessor. IEEE Micro, 19(2):24-36, March/April 1999.

• Nam Sung Kim, Todd Austin, David Blaauw, Trevor Mudge, Krisztian Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut Kandemir, and Vijaykrishnan Narayanan. Leakage current: Moore's law meets static power. IEEE Computer, 36(12):68-74, December 2003.

• J. Kin, M. Gupta, and W. Mangione-Smith. The filter cache: An energy efficient memory structure. In IEEE Micro. IEEE, 1997.

• Johnson Kin, Munish Gupta, and William H. Mangione-Smith. The filter cache: an energy efficient memory structure. In Proceedings of 30th Annual International Symposium on Microarchitecture, pages 184-193, December 1997.

• Jerzy Kolinski, Ram Chary, Andrew Henroid, and Barry Press. Building the Power-Efficient PC. Intel Press, 2001.

• Christoforos E. Kozyrakis and David A. Patterson. A new direction for computer architecture research. IEEE Computer, 31(11):24-32, November 1998.

• Chandra Krintz, Ye Wen, and Rich Wolski. Predicting program power consumption.

• Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makato Kako, Masaaki Kinugawa, Masakazu Kakumu, and Takayasu Sakurai. A 0.9-v, 150mhz, 10mw 4mm², 2-d discrete cosine transform core processor with variable threshold-voltage (vt) scheme. IEEE Journal of Solid-State Circuits, 31(11):1770-1779, November 1996.

• Peggy Laramie. Instruction level power analysis and low power design methodology of a microprocessor. Master's thesis, University of California, Berkeley, 199?

• Kai-Fu Lee, Hsiao-Wuen Hon, and Raj Reddy. An overview of the sphinx speech recognition system. IEEE, 1990.

• Chih-Chieh Lee, I-Cheng K Chen, and Trevor N Mudge. The bi-mode branch predictor. In Proceedings of the Thirteenth Annual IEEE/ACM International Symposium on Microarchitecture, pages 4-13, 1997.

• Dennis C Lee, Patrick J Crowley, Jean-Loup Baer, Thomas E Anderson, and Brian N Bershad. Execution characteristics of desktop applications on windows nt. In Proceedings of the 27th International Conference on Computer Architecture, 1998.

• Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, and Naehyuck Chang. An accurate instruction-level energy consumption model for embedded RISC processors. In LCTES/OM, pages 1-10, 2001.

• Charles Lefurgy, Mike Kistler, and Heather Hanson. Power sensor network.

• Charles Lefurgy, Peter Bird, I-Cheng Chen, and Trevor Mudge. Improving code density using compression techniques. In Proceedings of Micro-30, pages 194-203, Research Triangle Park, North Carolina, December 1997.

• Steve Leibson. Xscale (strongarm-2) muscles in. Microprocessor Report, 14(9), September 2000.

• Tao Li and Lizy John. Routine based os-aware microprocessor resource adaptation for run-time operating system power saving. In Proceedings of the 2003 International Symposium on Low Power Electronics and Design (ISLPED), pages 241-246, August 2003.

• Tao Li and Lizy John. Run-time modeling and estimation of operating system power consumption,. In Proceedings of the International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), pages 160 -- 171, August 2003.

• Hai Li, Chen-Yong Cher, T. N. Vijaykumar, and Kaushik Roy. Vsv: L2-miss-driven variable supply-voltage scaling for low power. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, pages 19 -- 28, December 2003.

• W. Lin, Steven Reinhardt, and Doug Burger. Reducing dram latencies with an integrated memory hierarchy design. In International Symposium on High Performance Computer Architecture, January 2001.

• Duke Liu and Christer Svensson. Power consumption estimation in CMOS VLSI chips. IEEE Journal of Solid-State Circuits, 29(6):663-660, June 1994.

• Jack L Lo, Luiz Andre Barroso, Susan J Eggers, Kourosh Gharacharloo, Henry M Levy, and Sujay S Parekh. An analysis of database workload performance on simultaneous multithreaded processors. In Proceedings of the 27th International Conference on Computer Architecture, 1998.

• E. Macii, M. Pedram, and F. Somenzi. High-level power modeling, estimation and optimization, 1997.

• Kennetth Mai, Timothy Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, and Mark Horowitz. Smart memories: A modular reconfigurable architecture. In ISCA 2000, June 2000.

• Hiroshi Makino, Yoshiki Tujihashi, Koji Nii, Chikayoshi Morishima, Yasuhi Hayakawa, Toru Shimizu, and Takahiko Arakawa. An auto-backgate-controlled MT-CMOS circuit. In Symposium on VLSI Circuits, pages 42-43, 1998.

• Srilatha Manne, Artur Klauser, and Dirk Grunwald. Pipeline gating: Speculation control for energy reduction. In Proceedings of the 25th Annual Symposium on Computer Architecture (ISCA), pages 132-141, 1998.

• Srilatha Manne, Artur Klauser, and Dirk Grunwald. Pipeline gating: Speculation control for energy reduction. In 25th International Symposium on Computer Architecture, pages 1-10, Jun 1998.

• Deborah T Marr, Frank Binns, David L. Hill, Glenn Hinton, David A. Koufaty, J. Alan Miller, and Michael Upton. Hyper-threading technology architecture and microarchitecture: A hypertext history. Intel Technology Journal, 6(1), February 2002.

• Thomas L. Martin and Daniel P. Siewiorek. The impact of battery capacity and memory bandwidth on cpu speed-setting: A case study. In ISLPED99, pages 200-205. ACM, 1999.

• Milo M. Martin, Amir Roth, and Charles Fischer. Exploiting dead value information. In Proceedings of 30th Annual International Symposium on Microarchitecture, pages 125-135, December 1997.

• M. Matson, D. Bailey, S. Bell, L. Biro, S. Butler, J. Clouser, J. Farrell, M. Gowan, D. Priore, and K. Wilcox. Circuit implementation of a 600mhz superscalar RISC microprocessor. In Proceedings of the International Conference on Computer Design, pages 104-110, 1998.

• Grant W. McFarland. CMOS Technology Scaling and Its Impact on Cache Delay. PhD thesis, Stanford University, June 1997.

• T. McPherson, R. Averill, D. Balazich, K. Barkley, S. Carey, Y. Chan, Y.H. Chan, R. Crea, A. Dansky, R. Dwyer, A. Haen, D. Hoffman, A. Jatkowski, M. Mayo, D. Merrill, T. McNamara, G. Northrop, J. Rawlins, L. Sigal, T. Slegel, and D. Webber. 760 mhz g6 s/390 microprocessor exploiting multiple V_t and copper interconnects. In International Solid-State Circuits Conference, pages 96-97, 2000.

• Motorola semiconductor products sector architectural brief: M*core microrisc engine, 1997.

• M*core: Processing interrupts, 1998.

• Trevor Mudge. Power: A first class design constraint. Computer, 34(4):52-57, April 2001.

• Subhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, pages 29 -- 38, December 2003.

• F. N. Najm. A survey of power estimation techniques in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994.

• Karthik Natarajan, Heather Hanson, Stephen W. Keckler, and Charles R. Moore. Microprocessor pipeline energy analysis. In Proceedings of the 2003 International Symposium on Low Power Electronics and Design (ISLPED), pages 282-287, August 2003.

• Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasuhi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, and Hisanori Hamano. A low power SRAM using auto-backgate-controlled MT-CMOS. In International Symposium on Low Power Electronics and Design, pages 293-298, 1998.

• Vojin G. Oklobdzija. Architectural tradeoffs for low power. In Power Driven Microarchitecture Workshop in conjunction with ISCA98. ISCA, 1998.

• Mark Oskin, Frederic T. Chong, and Matthrew Farrens. Hls: Combining statistical and symbolic simulation to guide microprocessor design. In ISCA 2000, June 2000.

• David Pan, H. Ren, and D. S. Kung. Sensitivity guided netweighting for placement driven synthesis. In To appear in Proc. International Symposium on Physical Design (ISPD), April 2004.

• D. Parikh, K. Skadron, Yan Zhang, M. Barcella, and M.R. Stan. Power issues related to branch prediction. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, pages 211 --222, 2002.

• Sanjay Jeram Patel, Daniel Holmes Friendly, and Yale N. Patt. Evaluation of design options for the trace cache fetch mechanism. IEEE Transactions on Computers, 48(2):435 -- 446, February 1999.

• Intel® pentium® 4 processor in the 478-pin package at 1.40 ghz, 1.50 ghz, 1.60 ghz, 1.70 ghz, 1.80 ghz, 1.90 ghz, and 2 ghz datasheet.

• Chuck Peplinski and Torsten Fink. A digital television receiver using a media processor, May 1999.

• M. Pertijs, A. Niederkorn, Xu Ma, B. McKillop, A. Bakker, and J. Huijsing. Cmos temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.5/spl deg/c from -50/spl deg/c to 120/spl deg/c. In International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), volume 1, pages 200 -- 488, 2003.

• F. Petrini and W. Feng. Efficient resource utilization on a massively parallel systems. In 7^th international conference on Advanced Computing and Communications, December 1999.

• F. Petrini and W. Feng. Scheduling with global information in distributed systems. In Proceedings of the IEEE International Conference on Distributed Computing Systems, April 2000.

• Fred Pollack. New microarchitectural challenges in the coming generations of cmos process technologies. slides from Fred Pollack's Micro32 keynote speech, November 1999.

• Dmitry Ponomarev, Gurhan Kucuk, and Kanad Ghose. Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. In 34th International Symposium on Microarchitecture, pages 90-101, Dec 2001.

• Michael Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, and T.N. Vijaykumar. Gated-V_dd: A circuit technique to reduce leakage in deep-submicron cache memories. In International Symposium on Low Power Electronics and Design, pages 90-95, 2000.

• David Albonesi Rajeev Balasubramonian, Alper Buyuktosunoglu, and Sandhya Dwarkadas. Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. In 33rd International Symposium on Microarchitecture. MICRO-33, December 2000.

• S. Rao, L. Alvisi, and H. Vin. Hybrid message-logging protocols for fast recovery. In Digest of FastAbstracts. The 28th International Symposium on Fault-Tolerant Computing, pages 41-42, Munich, Germany, June 1998.

• Sriram Rao, Lorenzo Alvisi, and Harrick M. Vin. Egida: An extensible toolkit for low-overhead fault-tolerance. In Symposium on Fault-Tolerant Computing, pages 48-55, 1999.

• Mosur K. Ravishankar. Efficient Algorithms for Speech Recognition. PhD thesis, School of Computer Science, Carnegie Mellon University, 1996.

• Glenn Reinman and Norm Jouppi. An integrated cache timing and power model, 1999. Unpublished document.

• Scott Rixner, William J. Daly, Ujval J. Kapasi, Brucek Khailany, Abelardo Lopez-Lagunas, Peter R. Mattson, and John D. Owens. A bandwidth-efficient architecture for media processing. In Proceedings of the 31st Annual International Symposium on Microarchitecture, pages 3-13, Dallas, Texas, November 1998.

• Evrven Rohou and Michael D. Smith. Dynamically managing processor temperature and power. In 2nd Workshop on FeedbackDirected Optimization, November 1999.

• Mendel Rosenblum, Edouard Bugnion, Stephen Alan Herrod, Emmett Witchel, and Anoop Gupta. The impact of architectural trends on operating system performance. In Proceedings of the 15th ACM Symposium on Operating Systems Principles, 1995.

• Eric Rotenberg, Steve Bennett, and Jim Smith. Trace cache: a low latency approach to high bandwidth instruction fetching. In Proceedings of the 29th Annual International Symposium on Microarchitecture. ACM, 1996.

• Kaushik Roy. Leakage power reduction in low-voltage CMOS designs. In International Conference on Electronics, Circuits and Systems, pages 167-73, 1998.

• Alexander I. Rudnicky, Stephen D. Reed, and Eric H. Thayer. Speechwear: A mobile speech system. In Proceeding of Fourth International Conference on Spoken Language Processing, pages 538-541, School of Computer Science, Carnegie Mellon University,5000 Forbes Avenue, Pittsburg, Pa 15213-3890, October 1996.

• Cosmin Rusu, Rami Melhem, and Daniel Mosse'. Maximizing the system value while satisfying time and energy cosntraints. In Proceedings of the IEEE Real-Time Systems Symposium, December 2002. also scheduled for IBM Journal of R&D.

• M. Sami, D. Sciuto, C. Silvano, and V. Zaccaria. Instruction level power estimation for embedded VLIW cores. In Proceedings of the eighth international workshop on Hardware/software codesign, pages 34-38, 2000.

• Jeff Scott, Lea Hwang Lee, Ann Chin, John Arends, and Bill Moyer. Designing the m*core m3 cpu architecture. In 1999 International Conference on Computer Design, Austin, Texas, October 1999.

• The national technology roadmap for semiconductors. Semiconductor Industry Association, 1999.

• Nat Seshan. High velociti processing. IEEE Signal Processing Magazine, 15(2):86-101, March 1998.

• T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, October 2002.

• F. Sijstermans, E.J.Pol, B. Riemans, K.Vissers, S.Rathnam, and G.Slavenburg. Design space exploration for future trimedia cpus. In International Conference on Acoustics, Speech and Signal Processing, pages 3137-3140, Seattle, Washington, May 1998.

• Amit Sinha and Anantha Chandrakasan. Jouletrack - a web based tool for software energy profiling. In Design Automation Conference, pages 220-225, 2001.

• Kevin Skadron, Pritpal S Ahuja, Margaret Martonosi, and Douglas W Clark. Branch prediction, instruction-window size, and cache size: Performance tradeoffs and simulation techniques. IEEE Transactions on Computers, 48(11), November 1999.

• Kevin Skadron, Tarek Abdelzaher, and Mircea R. Stan. Control-theoretic techniques and thermal-rc modeling for accurate and localized dynamic thermal management. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture. IEEE, 2002.

• K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-aware microarchitecture. In Proceedings of the 30th International Symposium on Computer Architecture, pages 2-13, June 2003.

• James E Smith. A study of branch prediction strategies. In 8th Annual International Symposium of Computer Architecture, 1981.

• Kimming So and Rudolph N. Rechtshaffen. Cache operations by mru change. IEEE Transactions on Computers, 37(6):700-109, July 1988.

• Gurindar S Sohi, Scott E Breach, and T N Vijaykumar. Multiscalar processors. In Proceedings of the 22nd International Symposium on Computer Architecture, 1995.

• Jim Smith Subbarao Palacharla, Norman Jouppi. Complexity-effective superscalar processors. In Proceedings ISCA 1997, 1997.

• Tensilica. Application specific microprocessor solutions, datasheet for xtensa v1, 1998. preliminary datasheet.

• Tensilica. Tensilica demo, October 1999. On-line demonstration.

• Tensilica. Tensilica: Technology, October 1999.

• Scott Thompson, Paul Packan, and Mark Bohr. Mos scaling: Transistor challenges for the 21st century. technical journal Q398, Intel Corporation, Portland Technology Development, Intel Corporatin, 1998.

• V. Tiwari, S. Malik, and A. Wolfe. Power analysis of embedded software: a first step towards software power minimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4):437-445, 1994.

• M. C. Toburen, T. M. Conte, and M. Reilly. Instruction scheduling for low power dissipation in high performance microprocessors. In Power Driven Microarchitecture Workshop in conjunction with ISCA'98, June 1998.

• Crusoe processor model tm5600 product brief.

• Efficeon processor tm8600.

• unknown. Majc architecture tutorial. Sun Microsystems White Paper, 1999.

• Madhavi Valluri, Lizy John, and Heather Hanson. System level issues: Exploiting compiler-generated schedules for energy savings in high-performance processors. In Proceedings of the 2003 International Symposium on Low Power Electronics and Design, pages 414-419, August 2003.

• Sivakumar Velusamy, Karthik Sankaranarayanan, Dharmesh Parikh, Tarek Abdelzaher, and Kevin Skadron. Adaptive cache decay using formal feedback control.

• Carlin Vieri, Isabel Yang, Anantha Chandrakasan, and Dimitri Antoniadis. SOIAS: Dynamically variable threshold SOI with active substrate. In International Symposium on Low Power Electronics, pages 86-87, 1995.

• N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim, and W. Ye. Energy-driven integrated hardware-software optimizations using simplepower. In ISCA 2000, June 2000.

• Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarsinghe, and Anant Agarwal. Baring it all to software: Raw machines. IEEE Computer, 1997.

• Frank Wang. A modified architecture for high-density mram. Computer Architecture News, 29(1):16-22, March 2001.

• Kathryn Wilcox and Srilatha Manne. Alpha processors: A history of power issues and a look to the future. In Cool Chips Tutorial: An Industrial Perspective on Low Power Processor Design, pages 16-37, 1999.

• Andrew Wolfe and Derek B.Noonburg. A superscalar 3d graphics engine. In Proceedings of the 32nd Annual International Symposium on Microarchitecture, Haifa, Israel, November 1999.

• C.C. Wu, C.H. Diaz, B.L. Lin, S.Z. Chang, C. C. Wang, JU. J. Liaw, C. H. Wang, K.K. Young, K.H. Lee, B.K. Liew, and J.Y.C. Sun. Ultra-low leakage 0.16um cmos for low-standby power applications. In Proceedings of the IEEE International Electron Devices Meeting, pages 671-6741, December 1999.

• Kyoji Yamashita and Shinji Odanaka. Interconnect scaling secenario. IEEE transactions on electron devices, 47(1):90-96, 2000.

• Chia-Lin Yang and Alvin R. Lebeck. Push vs. pull: Data movement for linked data structures. In Proceedings of the 2000 International Conference on Supercomputing, 2000.

• Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, and T.N. Vijaykumar. An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance caches. In International Symposium on High-Performance Computer Architecture, pages 147-157, 2001.

• Yibin Ye, Shekhar Borkar, and Vivek De. A new technique for standby leakage reduction in high-performance circuits. In Symposium on VLSI Circuits, pages 40-41, 1998.

• W. Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, and Mary Jane Irwin. The design and use of simplepower: a cycle-accurate energy estimation tool. In Design Automation Conference, pages 340-345, 2000.

• Norman K. Yeung, Yue-Hong Sutu, Terry Yi-Feng Su, Ed Tonguk Pak, Chia-Chi Chao, Shaila Akki, Dennis Da Yau, and Richard Lodenquai. The design of a 55 specint92 risc processor under 2w. In International Solid-State Circuits Conference, pages 206-207, 1994.

• Seung-Moon Yoo, Jose Renan, Michael Huang, and Josep Torrellas. Flexram architecture design parameters. Technical Report 1584, University of Illinois at Urbana-Champaign, October 2000.

• Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, and Thomas M. Conte. Adaptive mode-control: A static-power-efficient cache design. In International Conference on Parallel Architectures and Compilation Techniques, 2001.

• Victor V. Zyuban. Inherently Lower-Power High-Performance Superscalar Architectures. PhD thesis, University of Notre Dame, March 2000.