\documentstyle{article}
\newcommand{\is}{\setlength{\itemsep}{-1ex}}
\newcommand{\ts}{\setlength{\topsep}{-1ex}}
\newcommand{\hs}{\hspace*{1.5em}}
\addtolength{\topsep}{-1ex}
\parskip 1.3ex
\parindent 0em
\addtolength{\textheight}{3in}
\addtolength{\topmargin}{-1.5in}
\addtolength{\textwidth}{2in}
\addtolength{\oddsidemargin}{-1in}
\begin{document}
\begin{titlepage}

\begin{center}
{\bf CALL FOR PAPERS}                \\
\Large {\bf International Conference on \\
            Formal Methods in Computer-Aided Design (FMCAD'98)}\\
            Palo Alto, CA, USA                  \\
            4 -- 6 November 1998                   \\
            In cooperation with  IFIP WG 10.5
 \end{center}

{\bf Focus and Objectives:}\\ The International Conference on Formal
Methods in Computer-Aided Design '98 (FMCAD'98) is a forum for
presenting state-of-the-art tools and techniques based on formalized
reasoning for computer-aided design of hardware, and comes two years
after the previous (and first) event in the FMCAD series, which
received overwhelming response.
The location of the
conference provides a unique opportunity for researchers in the field
to interact with engineers from the Silicon Valley semiconductor and
CAD companies. In addition, FMCAD'98 will be held immediately prior
to ICCAD'98 for the convenience of people wanting to attend both
conferences.
The objective is to cover all relevant formal aspects
of work in computer-aided system design including verification,
synthesis and testing.
The conference will cover
original research in this area, as well as case studies, technology
transfer, and other practical experiments.
A special focus will be on tool demos and embedded tutorials.
It is intended to publish
the Proceedings in time for distribution at the conference in the
Springer LNCS series.  Specific technical areas of FMCAD'98 include,
but are not limited to:

$\bullet$ Hardware verification techniques
	based on model checking, theorem proving, and related or hybrid
	methods, \\
$\bullet$ Correct by construction approaches to hardware design, such as
   synthesis and transformation,\\
$\bullet$ Hybrid approaches that integrate synthesis and verification or
   different verification techniques,\\
$\bullet$ Integration of formal methods with CAD tools, such as for synthesis,
   simulation, design exploration, and testing,\\
$\bullet$ Formalized reasoning techniques supporting
	hardware- and system-level description languages,\\
$\bullet$ Case studies and application of formal methods in industry.

{\bf Invited Speakers:}\\*[.5ex]
$\bullet$ Ken McMillan, Cadence Berkeley Labs, USA \\
$\bullet$ Carl Seger, Intel Corporation, USA \\
$\bullet$ Richard Platek, Cornell University, and Consultant, ORA Corp., USA \\
$\bullet$ Amir Pnueli, Weizmann Institute, Israel

{\bf Papers:} 18-page, 12-point font for evaluation, with abstract.
Simultaneous submission
to other conferences or journals and submission of previously published
material are not allowed.

{\bf Tutorials and Tool Demos:} 7-page, 12-point font abstract for evaluation.
We encourage presentations of tools on a
suitable set of completely worked out examples.

{\bf Submit} your papers via the FMCAD web-page http://lal.cs.byu.edu/fmcad/.
Email to fmcad@lal.cs.byu.edu for paper and program inquiries.

{\bf Important Dates:}
\vspace{-1.5ex}
\begin{center}\begin{tabular*}{6in}{ll}
Submission deadline (firm)		&	{\bf April 20,} {\bf 1998}\\
Notification of acceptance	&		{\bf June 20,}  {\bf 1998}\\
Camera ready copy of accepted papers  &  {\bf  Aug 1,}          {\bf 1998}
\end{tabular*}
\end{center}

\vspace{-1ex}
\footnotesize
\begin{center}\begin{tabular}{lll}

\multicolumn{3}{l}{
{\normalsize {\bf General Chairs: Ganesh Gopalakrishnan (Univ. of Utah) and Phillip Windley (Brigham Young Univ.)} }}\\[1ex]

\multicolumn{3}{l}{
{\normalsize {\bf Local Arrangements: Jens Skakkeb{\ae}k (Stanford University)
} }}\\[1ex]

{\normalsize {\bf Program Committee:}}\\*[.5ex]

M. Aagaard (Intel, USA)         & M. Fujita (Fujitsu, USA)                     &T. Leonard (DEC, USA)\\
R. Bryant  (CMU, USA)           & S. German (IBM, USA)                         &T. Melham (Glasgow U, UK)\\
J. Burch   (Cadence, USA)       & T. Henzinger (Berkeley, USA)                 &M. Sheeran (Chalmers Tech U., Sweden)\\
A. Camilleri (HP, USA)          & R. Hojati (HDAC and Berkeley, USA)           &T. Shiple (Synopsys, USA)\\
E. Cerny  (U. Montreal, Canada) & A. Hu (UBC, Canada)                          &J. Skakkeb{\ae}k (Stanford U.)\\
S.-K. Chin   (Syracuse U., USA) & W. Hunt (IBM Austin, USA)                    &M. Srivas (SRI International, USA)\\
C.-T. Chou (Intel, USA)         & S. Johnson (Indiana U., USA)                 &R. Vemuri (U. Cinncinnati, USA)\\
F. Corella (HP, USA)            & C. Delgado Kloos (U. Carlos III, Spain)      &J. Van Tassel (Texas Instruments, USA)\\
L. Fix (Intel, Israel)          & T. Kropf (U. Karlsruhe, Germany)             &
\end{tabular}
\end{center}
\end{titlepage}
\end{document}