Vineet Kahlon

• Education 

• PhD in CS from UT Austin, Fall 2003
• MS in CS from UT Austin, Spring 1999 
• BTech in CSE from IIT Kanpur, Spring 1997
  

• Contact Information
  • Phone: (512) 694-1585
  • Email: [my-surname]@cs.utexas.edu or [my-surname]@nec-labs.com
  • Address: 17 Green St., Princeton, NJ 08542
    
    

• Research Interests

  Formal Verification, Concurrency, Program Analysis, Model Checking, Temporal Logic, Theorem Proving and Algorithm Design
  

• Papers
  


• Semantic Reduction of Thread Interleavings for Concurrent Programs. V. Kahlon, S. Sankaranarayan and A. Gupta Fifteenth International Conference on Tools and Algorithms for Construction and Analysis of Systems (TACAS), York, U.K.. 2009. 
• Parameterization as Abstraction: A Tractable Approach to the Dataflow Analysis of Concurrent Programs. V. Kahlon. Twenty Third Annual IEEE Symposium on Logic in Computer Science (LICS), Pittsburgh, USA. August 2008. ps
• Bootstrapping: A Technique for Scalable Flow and Context-Sensitive Pointer Alias Analysis. V. Kahlon. ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Tucson,  Arizona. June 2008. ps
  
• Peephole Partial Order Reduction C. Wang, Z. Yang, V. Kahlon and A. Gupta 14th International Conference on Tools and Algorithms for Construction and  Analysis of Systems (TACAS), Budapest, Hungary. April 2008. ps
  
• Fast and Accurate Static Data-Race Detection for Concurrent Programs V. Kahlon, Y. Yang, S. Sankaranarayan and A. Gupta. 19th International Conference on Computer Aided Verification (CAV), Berlin,  Germany. July 2007. ps
• On the Analysis of Interacting Pushdown Systems V. Kahlon and A. Gupta. The Thirty Fourth Annual Symposium on Principles of Programming Languages (POPL), Nice, France. January 2007. ps
• An Automata Theoretic Approach for Model Checking Threads for LTL Properties V. Kahlon and A. Gupta. Twenty First Annual IEEE Symposium on Logic in Computer Science (LICS), Seattle, USA. August 2006. ps
• Symbolic Model Checking of Concurrent Programs using Partial Orders and On-the-fly Transactions V. Kahlon, A. Gupta and N. Sinha. 18th International Conference on Computer Aided Verification (CAV), Seattle,  USA. August 2006. ps
  
• Reasoning about Threads Communicating via Locks V. Kahlon, F. Ivancic and A. Gupta. 17th International Conference on Computer Aided Verification (CAV), Edinburgh,  Scotland. July 2005. ps
  
• Parameterized Model Checking of Ring-based Message Passing Systems E.A. Emerson and V. Kahlon. Annual Conference for the European Association for Computer Science Logic (CSL), Karpacz,  Poland. September 2004. ps
  
• Exact and Efficient Verification of Parameterized Cache Coherence Protocols E. A. Emerson and V. Kahlon. 12th IFIP Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), L'Aquila,  Italy. October 2003. ps
  
• Model Checking Guarded Protocols E. A. Emerson and V. Kahlon. Eighteenth Annual IEEE Symposium on Logic in Computer Science (LICS), pp 361-370, Ottawa, Canada. June 2003. ps
• Rapid Parameterized Model Checking of Snoopy Cache Protocols E. A. Emerson and V. Kahlon. 9th International Conference on Tools and Algorithms for Construction and Analysis of Systems (TACAS), pp 144-159, Warsaw, Poland. April 2003. ps
  
• Model Checking Larage-scale and Parameterized Resource Allocation Systems E. A. Emerson and V. Kahlon. 8th International Conference on Tools and Algorithms for Construction and  Analysis of Systems (TACAS), pp 251-265, Grenoble, France. April 2002. ps
  
• Reducing Model Checking of the Many to the Few E. A. Emerson and V. Kahlon. 17th International Conference on Automated Deduction, pp 236-254, Pittsburgh PA. July 2000. ps