# A simple Unix Makefile
#
# You can run 'make -n <target-name>' to see what rules get 
# called for <target-name>, without the commands doing anything.
# If you give no target name, it defaults to the first explicit
# target, which is 'all'

# Define 'make variables' first

# C++ compiler
CXX	= g++
CXXFLAGS= -g

# C preprocessor (cpp) flags: 
# -I flag specifies include file paths
CPPFLAGS= -I.

# Loader flags. The loader is set to be the C++ compiler,
# not 'ld'. On some Unix systems, ld does not correctly
# link C++ object files unless the C++ compiler first does
# some pre-linking work.
LD	= $(CXX)

# LDFLAGS is sometimes set to -L/some/path or 
# -R/some/path for telling the linker where to 
# find non-standard libraries
LDFLAGS	=

# LIBS is usually set to special libraries, e.g., -lsocket 
# to link with libsocket.a for doing networking.
LIBS	=

# command used to automatically used to generate object 
# file dependency rules.
DEPEND	= gcc -MM

# The files making up your program
files	= main.C String.C
headers	= String.h
sources= $(headers) $(files)
objects= $(files:.C=.o)

# The name of the executable you are building. 
program	= myprog

# Any libraries you need to build.
libraries=

# implicit rule for converting a C++ file to an object file
# the $< builtin make variable means the <name>.C component
# of the target. This rule will generate <name>.o from a
# <name>.C, specified in a dependency rule, usually in
# Make.dep

.C.o:	
	$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c $<

# "phony" (i.e., non-file targets)
.PHONY:	all clean realclean submit depend

# Now, define all the "make rules" by defining targets and their
# dependencies. Usually, define the 'all' target and any 
# programs or libraries you want to build.

all:	$(libraries) $(program) 

# the $@ make variable means the target name, so $@ 
# evaluates to whatever $(program) is set to be.

$(program): $(objects)
	$(LD) $(objects) -o $@ $(LDFLAGS) $(LIBS)

# Explicit file dependency rules. You can get rid of these
# and use the impliciti .C.o rule above in conjunction with
# the depend rule below and the include directive to include
# the dependencies from the depend.rules file.

String.o:	String.C String.h
		$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c String.C

main.o:		main.C String.h
		$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c main.C

# cleanup
clean:
	rm -f *.o a.out core $(program) submit.uu

realclean:	clean
	rm -f *~ 

# Program submission. Scrub directory, remake Make.deps, and
# tar everything up into a uuencode file ready for emailing.
submit:	realclean depend README Makefile $(sources)
	tar cvf - ../prog1 | compress | uuencode prog1.tar.Z > submit.uu

# The depend rule to automatically generate the dependency rules
# for all .o files.  GNU gcc uses the -MM flag to generate
# these.  Check your C/C++ compiler to see if it has a similar
# flag you can use.

depend:	
	rm -f Make.dep
	$(DEPEND) $(files) > Make.dep

# The include directive will include Make.dep. If the include
# directive is supported with your version of make, 
# uncomment the line below that works. Otherwise, run
# make depend, and append Make.dep to this file manually.

# Sun, AIX, and GNU make use 'include <filename>'
#include Make.dep

# BSD Unix and Linux make use '.include <filename>'
#.include Make.dep