IBM Power Architcture Features

The PowerPC has several features that the compiler can use to improve the performance of generated code:

• Store-multiple instruction: makes saving registers faster, speeding up subroutine call.

• Multiple condition-code registers: better code can be generated for compound tests.

• Cache prefetch instruction: allows the CPU to start fetching memory before it is needed, avoiding cache miss delays.

• Superscalar architecture: 3 units (integer, float, branch) can execute simultaneously.

• Out-of-order execution: the processor can look ahead in the instruction stream for an instruction to execute. The compiler may move instructions to maximize this effect.

• Conditional branch instructions can indicate the ``expected'' outcome (branch or not branch). The processor can speculatively execute instructions in the expected path.